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1. 发明授权

US07033927B2 Apparatus and method for thermal isolation, circuit cooling and electromagnetic shielding of a wafer 有权
标题翻译：晶片的隔热，电路冷却和电磁屏蔽的装置和方法
公开(公告)号：US07033927B2
公开(公告)日：2006-04-25
申请号：US10872451
申请日：2004-06-22
申请人： Guy M. Cohen , Daniel C. Edelstein , Keith A. Jenkins , Chirag S. Patel , Lie Shan
发明人： Guy M. Cohen , Daniel C. Edelstein , Keith A. Jenkins , Chirag S. Patel , Lie Shan
IPC分类号： H01L21/4763
CPC分类号： H01L23/552 , H01L23/3677 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The disclosure relates to method and apparatus for isolating sensitive regions of a semiconductor device by providing a thermal path or an electromagnetic shield. The thermal path may include vias having different length, depth and configuration such that the thermal path between the two regions is lengthened. In addition, the vias may be fully or partially filled with an insulating material having defined conductive properties to further retard heat electromagnetic or heat transmission between the regions. In another embodiment, electrical isolation between two regions is achieved by etching a closed loop or an open loop trench at the border of the regions and filling the trench with a conductive material to provide proper termination of electromagnetic fields within the substrate.
摘要翻译：本公开涉及通过提供热路径或电磁屏蔽来隔离半导体器件的敏感区域的方法和装置。热路径可以包括具有不同长度，深度和构造的通孔，使得两个区域之间的热路径被延长。此外，通孔可以被完全或部分地填充有具有确定的导电性质的绝缘材料，以进一步延缓区域之间的热电磁或热传递。在另一个实施例中，通过在区域边界处蚀刻闭环或开环沟槽并用导电材料填充沟槽来实现两个区域之间的电隔离，以提供衬底内电磁场的适当终止。

2. 发明授权

US09728619B2 Generation of multiple diameter nanowire field effect transistors 有权
公开(公告)号：US09728619B2
公开(公告)日：2017-08-08
申请号：US13610266
申请日：2012-09-11
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/423 , B82Y10/00 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/66439 , H01L29/78696
摘要： A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.

3. 发明授权

US08921825B2 Nanowire field effect transistor device 有权
标题翻译：纳米线场效应晶体管器件
公开(公告)号：US08921825B2
公开(公告)日：2014-12-30
申请号：US13608089
申请日：2012-09-10
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/06 , H01L29/786 , H01L29/423 , B82Y10/00 , H01L29/66 , H01L29/775
CPC分类号： B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696 , Y10S977/938
摘要： A field effect transistor device includes a nanowire, a gate stack comprising a gate dielectric layer disposed on the nanowire, a gate conductor layer disposed on the dielectric layer and a substrate, and an active region including a sidewall contact portion disposed on the substrate adjacent to the gate stack, the side wall contact portion is electrically in contact with the nanowire.
摘要翻译：场效应晶体管器件包括纳米线，包括设置在纳米线上的栅极电介质层的栅极堆叠，设置在电介质层上的栅极导体层和衬底，以及包括设置在基板上的侧壁接触部分的有源区域，栅极堆叠，侧壁接触部分与纳米线电接触。

4. 发明授权

US08680510B2 Method of forming compound semiconductor 失效
标题翻译：形成化合物半导体的方法
公开(公告)号：US08680510B2
公开(公告)日：2014-03-25
申请号：US12824288
申请日：2010-06-28
申请人： Sarunya Bangsaruntip , Mikael Bjoerk , Guy M. Cohen , Heike E. Riel , Heinz Schmid
发明人： Sarunya Bangsaruntip , Mikael Bjoerk , Guy M. Cohen , Heike E. Riel , Heinz Schmid
IPC分类号： H01L29/12 , H01L33/02
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/0243 , H01L21/02521 , H01L21/02543 , H01L21/02603 , H01L21/02658 , H01L29/0673 , H01L29/068 , H01L29/125 , H01L29/42392 , H01L29/775 , H01L29/778 , H01L29/78681 , H01L29/78696
摘要： A method of forming a semiconductor is provided and includes patterning a pad and a nanowire onto a wafer, the nanowire being substantially perpendicular with a pad sidewall and substantially parallel with a wafer surface and epitaxially growing on an outer surface of the nanowire a secondary layer of semiconductor material, which is lattice mismatched with respect to a material of the nanowire and substantially free of defects.
摘要翻译：提供了形成半导体的方法，并且包括将衬垫和纳米线图案化到晶片上，所述纳米线基本上与衬垫侧壁垂直并且基本上平行于晶片表面并且外延生长在纳米线的外表面上，半导体材料，其相对于纳米线的材料而晶格失配并且基本上没有缺陷。

5. 发明申请

US20140014904A1 Replacement Contacts for All-Around Contacts 有权
标题翻译：全方位联系人的替换联系人
公开(公告)号：US20140014904A1
公开(公告)日：2014-01-16
申请号：US13558532
申请日：2012-07-26
申请人： Guy M. Cohen , Michael A. Guillorn
发明人： Guy M. Cohen , Michael A. Guillorn
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/413 , H01L29/42364 , H01L29/66439
摘要： In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device.
摘要翻译：一方面，提供一种FET器件。 FET器件包括衬底; 衬底上的半导体材料; 所述衬底上的至少一个栅极围绕用作所述器件的沟道区的所述半导体材料的一部分，其中从所述栅极延伸的所述半导体材料的部分用作所述器件的源极和漏极区域，并且其中所述源极和器件的漏极区域从衬底移位; 覆盖栅极和半导体材料的器件上的平坦化电介质; 以及延伸穿过平坦化电介质并且围绕器件的源极和漏极区域的触点。

6. 发明授权

US08574969B2 CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins 失效
标题翻译：具有沟道P-FinFET和沟道N-FinFET的CMOS具有不同的晶体取向和平行鳍片
公开(公告)号：US08574969B2
公开(公告)日：2013-11-05
申请号：US13560322
申请日：2012-07-27
申请人： Guy M. Cohen , Katherine L. Saenger
发明人： Guy M. Cohen , Katherine L. Saenger
IPC分类号： H01L21/00
CPC分类号： H01L27/0924 , H01L21/34 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： An integrated circuit fabrication apparatus is configured to fabricate an integrated circuit with at least one p-FinFET device and at least one n-FinFET device. A bonding control processor is configured to bond a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation. A material growth processor is configured to form a volume of material extending through the first silicon layer from the second layer up to the surface of first layer. The material has a crystalline orientation that substantially matches the crystalline orientation of second layer. An etching processor is configured to selectively etch areas of the surface of the first layer that are outside of the region to create a first plurality of fins and areas inside the region to create a second plurality of fins.
摘要翻译：集成电路制造装置被配置为制造具有至少一个p-FinFET器件和至少一个n-FinFET器件的集成电路。键合控制处理器被配置为将具有第一晶体取向的第一硅层与具有不同于第一晶体取向的第二晶体取向的第二硅层结合。材料生长处理器被配置为形成从第二层延伸穿过第一硅层到第一层的表面的材料体积。该材料具有基本上与第二层的晶体取向一致的结晶取向。蚀刻处理器被配置为选择性地蚀刻位于该区域外部的第一层的表面的区域，以在该区域内形成第一多个散热片和区域，以产生第二多个翅片。

7. 发明授权

US08563369B2 CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins 有权
标题翻译：具有沟道P-FinFET和沟道N-FinFET的CMOS具有不同的晶体取向和平行鳍片
公开(公告)号：US08563369B2
公开(公告)日：2013-10-22
申请号：US13560340
申请日：2012-07-27
申请人： Guy M. Cohen , Katherine L. Saenger
发明人： Guy M. Cohen , Katherine L. Saenger
IPC分类号： H01L21/00
CPC分类号： H01L27/0924 , H01L21/34 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： A method for fabricating an integrated circuit with at least one p-FinFET device and at least one n-FinFET device. The method includes bonding a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation. A first plurality of fins and a second plurality of fins are created. A spacer is formed around each fin in the first plurality of fins and second plurality of fins. A set of regions of the second layer between each fin in the first plurality of fins and the second plurality of fins are recessed to form a base with exposed sidewalls under each fin in the first plurality of fins and the second plurality of fins. The base under each fin and a set of exposed regions between each fin is oxidized.
摘要翻译：一种用至少一个p-FinFET器件和至少一个n-FinFET器件制造集成电路的方法。该方法包括将具有第一晶体取向的第一硅层与具有不同于第一晶体取向的第二晶体取向的第二硅层结合。产生第一多个翅片和第二多个翅片。在第一多个翅片和第二多个翅片中的每个翅片周围形成间隔件。在第一多个翅片中的每个翅片和第二多个翅片之间的第二层的一组区域被凹入以在第一多个翅片和第二多个翅片中的每个翅片下方形成具有暴露的侧壁的底部。每个翅片下面的基底和每个翅片之间的一组暴露区域被氧化。

8. 发明授权

US08455334B2 Planar and nanowire field effect transistors 失效
标题翻译：平面和纳米线场效应晶体管
公开(公告)号：US08455334B2
公开(公告)日：2013-06-04
申请号：US12631342
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L21/84
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66772
摘要： A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region.
摘要翻译：一种用于形成集成电路的方法，所述方法包括形成悬置在绝缘体衬底上的第一纳米线，所述第一纳米线附接到绝缘体上的第一绝缘体（SOI）焊盘区域和设置在所述绝缘体衬底上的第二SOI焊盘区域，布置在绝缘体基板上的第二纳米线，其连接到设置在绝缘体基板上的第三SOI焊盘区域和第四SOI焊盘区域，以及SOI板状区域，其设置在绝缘体基板上，并且形成围绕部分的第一栅极的第一纳米线，第二纳米线的一部分上的第二栅极和SOI板区域的一部分上的第三栅极。

9. 发明授权

US08308968B2 Monolithic high aspect ratio nano-size scanning probe microscope (SPM) tip formed by nanowire growth 有权
公开(公告)号：US08308968B2
公开(公告)日：2012-11-13
申请号：US12536156
申请日：2009-08-05
申请人： Guy M. Cohen , Hendrik F. Hamann
发明人： Guy M. Cohen , Hendrik F. Hamann
IPC分类号： G01Q30/00
CPC分类号： G01Q70/12 , G01Q60/22
摘要： A scanning probe where the micromachined pyramid tip is extended by the growth of an epitaxial nanowire from the top portion of the tip is disclosed. A metallic particle, such as gold, may terminate the nanowire to realize an apertureless near-field optical microscope probe.

10. 发明申请

US20120205626A1 SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP 有权
标题翻译：半导体芯片与基于图形的设备在芯片的互连结构中
公开(公告)号：US20120205626A1
公开(公告)日：2012-08-16
申请号：US13027797
申请日：2011-02-15
申请人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung
发明人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L21/02527 , H01L29/1606 , H01L29/41766 , H01L29/42356 , H01L29/66431 , H01L29/778 , H01L2924/00013 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.
摘要翻译：半导体结构包括包含其中包含的至少一个第一导电区域的第一电介质材料。该结构还包括位于第一介电材料顶部的至少一个含石墨烯的半导体器件。所述至少一个含石墨烯的半导体器件包括覆盖并与第一导电区直接相连的石墨烯层。所述结构还包括覆盖所述至少一个含石墨烯的半导体器件和所述第一电介质材料的部分的第二电介质材料。第二电介质材料包括其中包含的至少一个第二导电区域，并且至少一个第二导电区域与至少一个含石墨烯的半导体器件的导电元件接触。

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