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1. 发明申请

US20120205626A1 SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP 有权
标题翻译：半导体芯片与基于图形的设备在芯片的互连结构中
公开(公告)号：US20120205626A1
公开(公告)日：2012-08-16
申请号：US13027797
申请日：2011-02-15
申请人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung
发明人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L21/02527 , H01L29/1606 , H01L29/41766 , H01L29/42356 , H01L29/66431 , H01L29/778 , H01L2924/00013 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.
摘要翻译：半导体结构包括包含其中包含的至少一个第一导电区域的第一电介质材料。该结构还包括位于第一介电材料顶部的至少一个含石墨烯的半导体器件。所述至少一个含石墨烯的半导体器件包括覆盖并与第一导电区直接相连的石墨烯层。所述结构还包括覆盖所述至少一个含石墨烯的半导体器件和所述第一电介质材料的部分的第二电介质材料。第二电介质材料包括其中包含的至少一个第二导电区域，并且至少一个第二导电区域与至少一个含石墨烯的半导体器件的导电元件接触。

2. 发明授权

US08877340B2 Graphene growth on a non-hexagonal lattice 有权
标题翻译：非六方晶格上的石墨烯生长
公开(公告)号：US08877340B2
公开(公告)日：2014-11-04
申请号：US12844029
申请日：2010-07-27
申请人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
发明人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
IPC分类号： B32B9/00
CPC分类号： H01L21/02527 , B82Y30/00 , B82Y40/00 , C01B32/188 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02516 , Y10T428/30
摘要： A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.
摘要翻译：在具有非六边形对称性的结晶表面上形成石墨烯层。晶体表面可以是单晶半导体碳化物层的表面。单晶半导体碳化物层的非六边形对称表面在超高真空环境中在升高的温度下退火以形成石墨烯层。在退火过程中，单晶半导体碳化物层的非六边形表面上的半导体原子对碳原子有选择性的蒸发。随着半导体原子被选择性地去除，半导体 - 碳合金层表面上的碳浓度增加。尽管半导体 - 碳合金层的表面具有非六边形对称性，但剩余的碳原子可以聚结形成具有六边形对称性的石墨烯层。

3. 发明申请

US20120028052A1 GRAPHENE GROWTH ON A NON-HEXAGONAL LATTICE 有权
公开(公告)号：US20120028052A1
公开(公告)日：2012-02-02
申请号：US12844029
申请日：2010-07-27
申请人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
发明人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
IPC分类号： B32B17/06 , H01L21/20
CPC分类号： H01L21/02527 , B82Y30/00 , B82Y40/00 , C01B32/188 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02516 , Y10T428/30
摘要： A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.

4. 发明申请

US20120319078A1 GRAPHENE GROWTH ON A NON-HEXAGONAL LATTICE 审中-公开
标题翻译：非黑龙江地区的石墨生长
公开(公告)号：US20120319078A1
公开(公告)日：2012-12-20
申请号：US13596152
申请日：2012-08-28
申请人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
发明人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
IPC分类号： H01L29/06 , B82Y99/00
CPC分类号： H01L21/02527 , B82Y30/00 , B82Y40/00 , C01B32/188 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02516 , Y10T428/30
摘要： A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.
摘要翻译：在具有非六边形对称性的结晶表面上形成石墨烯层。晶体表面可以是单晶半导体碳化物层的表面。单晶半导体碳化物层的非六边形对称表面在超高真空环境中在升高的温度下退火以形成石墨烯层。在退火过程中，单晶半导体碳化物层的非六边形表面上的半导体原子对碳原子有选择性的蒸发。随着半导体原子被选择性地去除，半导体 - 碳合金层表面上的碳浓度增加。尽管半导体 - 碳合金层的表面具有非六边形对称性，但剩余的碳原子可以聚结形成具有六边形对称性的石墨烯层。

5. 发明授权

US09413075B2 Graphene based structures and methods for broadband electromagnetic radiation absorption at the microwave and terahertz frequencies 有权
公开(公告)号：US09413075B2
公开(公告)日：2016-08-09
申请号：US13523182
申请日：2012-06-14
申请人： Phaedon Avouris , Alberto V. Garcia , Chun-Yung Sung , Fengnian Xia , Hugen Yan
发明人： Phaedon Avouris , Alberto V. Garcia , Chun-Yung Sung , Fengnian Xia , Hugen Yan
IPC分类号： H01Q17/00
CPC分类号： H01Q17/00
摘要： Structures and methods for cloaking an object to electromagnetic radiation at the microwave and terahertz frequencies include disposing a plurality of graphene sheets about the object. Intermediate layers of a transparent dielectric material can be disposed between graphene sheets to optimize the performance. In other embodiments, the graphene can be formulated into a paint formulation or a fabric and applied to the object. The structures and methods absorb at least a portion of the electromagnetic radiation at the microwave and terabyte frequencies.

6. 发明授权

US09174413B2 Graphene based structures and methods for shielding electromagnetic radiation 有权
公开(公告)号：US09174413B2
公开(公告)日：2015-11-03
申请号：US13523178
申请日：2012-06-14
申请人： Phaedon Avouris , Alberto Valdes Garcia , Chun-Yung Sung , Fengnian Xia , Hugen Yan
发明人： Phaedon Avouris , Alberto Valdes Garcia , Chun-Yung Sung , Fengnian Xia , Hugen Yan
IPC分类号： F21V9/00 , G02B5/02 , G02C7/10 , G02F1/361 , G03B1/00 , H05K9/00 , B32B9/04 , B82Y30/00 , C23C16/00
CPC分类号： H05K9/0088 , B32B9/04 , B32B37/18 , B32B2457/00 , B82Y30/00 , H05K9/0081 , Y10T156/10
摘要： Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing highly doped graphene sheets about the object to be shielded. The highly doped graphene sheets may have a dopant concentration greater than >1e1013 cm−2, which is effective to reflect the electromagnetic radiation or a dopant concentration of 1e1013 cm−2>n>0 cm−2, which is effective to absorb the electromagnetic radiation.

7. 发明授权

US07960263B2 Amorphization/templated recrystallization method for hybrid orientation substrates 有权
标题翻译：混合取向基板的非晶化/模板重结晶方法
公开(公告)号：US07960263B2
公开(公告)日：2011-06-14
申请号：US12767261
申请日：2010-04-26
申请人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/20
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽限定的非晶化Si区域的边缘产生“角部缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

8. 发明授权

US07678622B2 Semiconductor method and device with mixed orientation substrate 有权
标题翻译：具有混合取向衬底的半导体方法和器件
公开(公告)号：US07678622B2
公开(公告)日：2010-03-16
申请号：US11868001
申请日：2007-10-05
申请人： Jiang Yan , Chun-Yung Sung , Danny Pak-Chum Shum , Alois Gutmann
发明人： Jiang Yan , Chun-Yung Sung , Danny Pak-Chum Shum , Alois Gutmann
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207 , H01L29/045 , H01L29/78687
摘要： In a method of forming a semiconductor device, a wafer includes a first semiconductor region of a first crystal orientation and a second semiconductor region of a second crystal orientation. Insulating material is formed over the wafer. A first portion of the insulating material is removed to expose the first semiconductor region and a second portion of the insulating material is removed to expose the second semiconductor region. Semiconductor material of the first crystal orientation is epitaxially grown over the exposed first semiconductor region and semiconductor material of the second crystal orientation is epitaxially grown over the exposed second semiconductor region.
摘要翻译：在形成半导体器件的方法中，晶片包括第一晶体取向的第一半导体区域和第二晶体取向的第二半导体区域。在晶片上形成绝缘材料。除去绝缘材料的第一部分以暴露第一半导体区域，并且去除绝缘材料的第二部分以暴露第二半导体区域。在暴露的第一半导体区域上外延生长第一晶体取向的半导体材料，并且在暴露的第二半导体区域上外延生长第二晶体取向的半导体材料。

9. 发明申请

US20090309136A1 SEA-OF-FINS STRUCTURE OF A SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATION 有权
标题翻译：半导体基板的海绵结构和制造方法
公开(公告)号：US20090309136A1
公开(公告)日：2009-12-17
申请号：US12535007
申请日：2009-08-04
申请人： Howard H. Chen , Louis C. Hsu , Jack A. Mandelman , Chun-Yung Sung
发明人： Howard H. Chen , Louis C. Hsu , Jack A. Mandelman , Chun-Yung Sung
IPC分类号： H01L27/10 , H01L21/8232
CPC分类号： H01L21/823437 , H01L21/823412 , H01L21/823431 , H01L27/1211 , H01L29/66795 , H01L29/66803 , H01L29/785 , Y10S977/734 , Y10S977/742 , Y10S977/749 , Y10S977/815 , Y10S977/955
摘要： A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.
摘要翻译：一种半导体器件和半导体器件的制造方法，其中所述方法包括在衬底上形成多个用于定制鳍状场效应晶体管（FinFET）器件形成的平坦化翅片体; 在所述多个翅片体中的每一个周围形成氮化物间隔物; 在每个翅片体之间形成隔离区域; 并用保护膜涂覆多个翅片体，氮化物间隔物和隔离区域。制造的半导体器件适用于定制应用中作为定制的半导体器件。

10. 发明授权

US07615816B2 Buried plate structure for vertical dram devices 失效
标题翻译：埋地板结构用于垂直放映装置
公开(公告)号：US07615816B2
公开(公告)日：2009-11-10
申请号：US11692473
申请日：2007-03-28
申请人： Kangguo Cheng , Ramachandra Divakaruni , Chun-Yung Sung
发明人： Kangguo Cheng , Ramachandra Divakaruni , Chun-Yung Sung
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10864 , H01L27/1087 , H01L29/945
摘要： A buried plate region for a semiconductor memory storage capacitor is self aligned with respect to an upper portion of a deep trench containing the memory storage capacitor.
摘要翻译：用于半导体存储器存储电容器的掩埋板区域相对于包含存储器存储电容器的深沟槽的上部自对准。

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