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    • 1. 发明申请
    • Process for producing a layer arrangement, and layer arrangement for use as a dual-gate field-effect transistor
    • 用于制造层布置的方法和用作双栅极场效应晶体管的层布置
    • US20060027881A1
    • 2006-02-09
    • US11178251
    • 2005-07-08
    • Gurkan IlicaliRichard LuykenWolfgang Roesner
    • Gurkan IlicaliRichard LuykenWolfgang Roesner
    • H01L29/76
    • H01L29/6656H01L29/66484H01L29/7831
    • A process for producing a layer arrangement, which layer arrangement allows a dual gate field-effect transistor to be formed. In this process, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate. A first semiconductor layer is formed on the sacrificial layer, and a first electrically insulating layer is formed on the first semiconductor layer. An electrically conductive layer is formed on the first electrically insulating layer, which electrically conductive layer is laterally patterned. The first electrically insulating layer, the sacrificial layer and the first semiconductor layer are jointly laterally patterned using the laterally patterned electrically conductive layer as a mask. Furthermore, a semiconductor structure is formed adjacent to side walls of the patterned sacrificial layer and of the patterned first semiconductor layer. A substrate is secured over the patterned electrically conductive layer, and material of the auxiliary substrate is removed, so that the sacrificial layer is uncovered. Furthermore, the sacrificial layer is selectively removed, so as to form a trench, and a second electrically insulating layer is formed in the trench, then an electrically conductive structure is formed on this second electrically insulating layer.
    • 一种制造层布置的方法,该层布置允许形成双栅场效应晶体管。 在该方法中,在辅助基板上形成多孔硅层作为牺牲层。 在牺牲层上形成第一半导体层,在第一半导体层上形成第一电绝缘层。 在第一电绝缘层上形成导电层,该导电层被横向图案化。 使用横向图案化的导电层作为掩模,共同地横向图案化第一电绝缘层,牺牲层和第一半导体层。 此外,半导体结构邻近图案化牺牲层和图案化的第一半导体层的侧壁形成。 将衬底固定在图案化的导电层上,并且去除辅助衬底的材料,使得牺牲层未被覆盖。 此外,选择性地去除牺牲层以形成沟槽,并且在沟槽中形成第二电绝缘层,然后在该第二电绝缘层上形成导电结构。
    • 8. 发明申请
    • Semiconductor memory component
    • 半导体存储器组件
    • US20060267082A1
    • 2006-11-30
    • US11438883
    • 2006-05-23
    • Franz HofmannRichard LuykenWolfgang RoesnerMichael SpechtMartin Staedele
    • Franz HofmannRichard LuykenWolfgang RoesnerMichael SpechtMartin Staedele
    • H01L29/76
    • H01L27/108H01L27/10802H01L27/1203
    • A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.
    • 半导体存储器组件包括至少一个存储单元。 存储单元包括由体区,漏区和源区组成的半导体本体,栅电介质和栅电极。 主体区域包括第一导电类型和源极和漏极区域之间的凹陷,并且源极和漏极区域包括第二导电类型。 栅电极至少部分地布置在凹陷中,并且通过栅极电介质与主体,源极和漏极区绝缘。 体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。 第一连续区域邻接漏极区域,凹陷部分和源极区域,并且第二区域布置在第一区域下方并与第一区域相邻。