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    • 2. 发明申请
    • Direct Smelting Plant and Process
    • 直接冶炼厂和工艺
    • US20070272058A1
    • 2007-11-29
    • US10576852
    • 2004-10-16
    • Andreas OrthDavid LeighPeter Burke
    • Andreas OrthDavid LeighPeter Burke
    • C21B15/00C22B3/02
    • F27B3/18C21B5/023C21B13/00C21B13/0013C21B13/143C21C5/567F27D13/00Y02P10/216
    • The present invention relates to a direct smelting plant and a direct smelting process for producing molten metal from a metalliferous feed material, such as ores, partly reduced ores, and metal-containing waste streams, the latter of which comprising the steps of (a) pretreating metalliferous feed material in a pretreatment unit and producing pretreated feed material having a temperature of at least 200° C., (b) storing pretreated metalliferous feed material having a temperature of at least 200° C. under pressure in a hot feed material storage means, (c) transferring pretreated metalliferous feed material having a temperature of at least 200° C. under pressure in a hot feed material transfer line to a solids delivery means of a direct smelting vessel, and (d) delivering pretreated metalliferous feed material into the direct smelting vessel and smelting metalliferous feed material to molten metal in the vessel.
    • 本发明涉及一种直接熔炼设备和用于从含金属的原料如矿石,部分还原的矿石和含金属的废物流中生产熔融金属的直接熔炼方法,后者包括以下步骤:(a) 在预处理单元中预处理含金属进料,并生产温度至少为200℃的预处理进料;(b)在热进料材料储存器中储存温度至少为200℃的预处理含金属进料 是指(c)在热进料输送管线中将压力为至少200℃的预处理的含金属进料传送到直接熔炼容器的固体输送装置,以及(d)将预处理的含金属进料输送到 直接熔炼容器和冶炼含金属进料到容器中的熔融金属。
    • 4. 发明授权
    • Method for fabricating planar semiconductor wafers
    • 制造平面半导体晶圆的方法
    • US07179736B2
    • 2007-02-20
    • US10966074
    • 2004-10-14
    • Byung-Sung Leo KwakPeter BurkeSey-Shing Sun
    • Byung-Sung Leo KwakPeter BurkeSey-Shing Sun
    • H01L21/4763
    • H01L21/76877C25D5/18C25D7/123H01L21/2885H01L21/7684
    • The present invention relates to a method of fabricating planar semiconductor wafers. The method comprises forming a dielectric layer on a semiconductor wafer surface, the semiconductor wafer surface having vias, trenches and planar regions. A barrier and seed metal layer is then formed on the dielectric layer. The wafer is next place in a plating bath that includes an accelerator, which tends to collect in the vias and trenches to accelerate the rate of plating in these areas relative to the planar regions of the wafer. After the gapfill point is reached, the plating is stopped by removing the plating bias on wafer. An equilibrium period is then introduced into the process, allowing higher concentrations of accelerator additives and other components of the bath)] above the via and trench regions to equilibrate in the plating bath. The bulk plating on the wafer is resumed after equilibration. Over-plating on the wafer in the areas of the vias and trenches is therefore avoided, resulting in a more planar metallization layer on the wafer, without the use of a leveler additive which adversely affects the gapfill capability.
    • 本发明涉及一种制造平面半导体晶片的方法。 该方法包括在半导体晶片表面上形成电介质层,该半导体晶片表面具有通孔,沟槽和平面区域。 然后在电介质层上形成阻挡层和种子金属层。 晶片是包含加速器的镀液中的下一个位置,该加速器倾向于在通路和沟槽中收集,以加速相对于晶片的平面区域在这些区域中的电镀速率。 达到间隙填充点后,通过去除晶片上的电镀偏压来停止电镀。 然后在该过程中引入平衡时段,允许较高浓度的促进剂添加剂和浴中的其它组分)]在通孔和沟槽区域上方在电镀浴中平衡。 平衡后恢复晶片上的块体电镀。 因此避免了在通孔和沟槽区域上的晶片上的过电镀,导致晶片上更平面的金属化层,而不使用不利地影响间隙填充能力的矫直添加剂。
    • 5. 发明申请
    • Self-aligned cell integration scheme
    • 自对准单元集成方案
    • US20060281256A1
    • 2006-12-14
    • US11312849
    • 2005-12-20
    • Richard CarterHemanshu BhattShiqun GuPeter BurkeJames ElmerSey-Shing SunByung-Sung KwakVerne Hornback
    • Richard CarterHemanshu BhattShiqun GuPeter BurkeJames ElmerSey-Shing SunByung-Sung KwakVerne Hornback
    • H01L21/336
    • H01L51/0018B82Y10/00H01L27/283H01L51/0048H01L51/0545Y10S977/742
    • A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
    • 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层,从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层,蚀刻介质层下方的夹层,产生电介质层的重叠,并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外,蚀刻间隔层。 除了夹持层,电介质层和间隔层中的至少一个的部分以外,蚀刻纳米管层,从而导致夹紧层之间的自对准,与电介质层的重叠,间隔层, 和纳米管层。