专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4956307A Thin oxide sidewall insulators for silicon-over-insulator transistors 失效
标题翻译：用于硅绝缘体晶体管的薄氧化物侧壁绝缘体
公开(公告)号：US4956307A
公开(公告)日：1990-09-11
申请号：US269803
申请日：1988-11-10
申请人： Gordon P. Pollack , Mishel Matloubian , Ravishankar Sundaresan
发明人： Gordon P. Pollack , Mishel Matloubian , Ravishankar Sundaresan
IPC分类号： G21F1/08 , H01L21/321 , H01L21/336 , H01L27/12 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/32105 , H01L29/4908 , Y10S257/906 , Y10S438/911 , Y10S438/953
摘要： A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa's insulating region (46). This oxidizable layer (56) is then anisotropically etched, resulting in oxidizable sidewalls (60). An optional foot (70) may be formed at the bottom edge of the oxidizable sidewalls (76). These oxidizable sidewalls (76) are then oxidized, resulting in a pure oxide sidewall (64). The gate (66) is then formed over the pure oxide sidewalls (64) and a gate oxide (62).
摘要翻译：提供了具有覆盖掩埋氧化物（42）的半导体台面（40）的绝缘体上硅晶体管。绝缘区域（50）形成在半导体台面（40）的侧面。在台面绝缘区域（46）之上形成可氧化层（56）。然后对该可氧化层（56）进行各向异性蚀刻，得到可氧化的侧壁（60）。可选的脚（70）可以形成在可氧化侧壁（76）的底部边缘处。然后，这些可氧化的侧壁（76）被氧化，产生纯氧化物侧壁（64）。然后，在纯氧化物侧壁（64）和栅极氧化物（62）上形成栅极（66）。

2. 发明授权

US5120675A Method for forming a trench within a semiconductor layer of material 失效
标题翻译：在材料的半导体层内形成沟槽的方法
公开(公告)号：US5120675A
公开(公告)日：1992-06-09
申请号：US531997
申请日：1990-06-01
申请人： Gordon P. Pollack
发明人： Gordon P. Pollack
IPC分类号： H01L21/308 , H01L21/762
CPC分类号： H01L21/76264 , H01L21/3085 , H01L21/76281 , H01L21/76283
摘要： A method and structure for forming a trench within a semiconductor layer (12) of material is provided. A first mask structure comprising a third insulating layer (20) and a fourth insulating layer (22) is formed adjacent a semiconductor layer (12). Sidewall spacers comprising a first and second portion (30) and (32) are formed along the sidewall (25) of layers (20) and (22) and extending outwardly therefrom. A second mask structure comprising a field insulating region (36) is formed adjacent first sidewall spacer portions (30) and along semicondcutor layer (12). The foot portions (34) of first sidewall spacer portions (30) are removed thereby defining an exposed area (38) between the first mask structure and second mask structure. A trench (40) may then be formed between the two mask structures and filled with dielectrical material in order to isolate a semiconductor mesa (42) from semiconductor regions (44a) and 44b).
摘要翻译：提供了一种用于在半导体层（12）内形成沟槽的方法和结构。在半导体层（12）附近形成包括第三绝缘层（20）和第四绝缘层（22）的第一掩模结构。包括第一和第二部分（30）和（32）的侧壁间隔物沿着层（20）和（22）的侧壁（25）形成并从其向外延伸。包括场绝缘区域（36）的第二掩模结构邻近第一侧壁间隔部分（30）并且沿半切割层（12）形成。去除第一侧壁间隔部分（30）的脚部（34），从而限定第一掩模结构和第二掩模结构之间的暴露区域（38）。然后可以在两个掩模结构之间形成沟槽（40），并且填充有介电材料，以便将半导体台面（42）与半导体区域（44a）和44b隔离开。

3. 发明授权

US4580330A Integrated circuit isolation 失效
标题翻译：集成电路隔离
公开(公告)号：US4580330A
公开(公告)日：1986-04-08
申请号：US621019
申请日：1984-06-15
申请人： Gordon P. Pollack , Clarence W. Teng , William R. Hunter , Christopher Slawinski , Robert R. Doering
发明人： Gordon P. Pollack , Clarence W. Teng , William R. Hunter , Christopher Slawinski , Robert R. Doering
IPC分类号： H01L29/78 , H01L21/32 , H01L21/76 , H01L21/762 , H01L29/06
CPC分类号： H01L29/0638 , H01L21/32 , H01L21/76232 , Y10S148/05
摘要： An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.
摘要翻译：一种集成电路隔离技术，其中通过在将第二氮化物（防止侵入的侧壁氮化物）添加到第一氮化物（覆盖护城河区域）之前执行底切和回填来改进现有技术的氮化物 - 侧壁方法。因此，使两个氮化物之间的对接更牢固，并且不会发生在护环氮化物和侧壁氮化物之间的对接接合处的局部鸟鸣。

4. 发明授权

US5240512A Method and structure for forming a trench within a semiconductor layer of material 失效
标题翻译：在材料的半导体层内形成沟槽的方法和结构
公开(公告)号：US5240512A
公开(公告)日：1993-08-31
申请号：US857041
申请日：1992-03-24
申请人： Gordon P. Pollack
发明人： Gordon P. Pollack
IPC分类号： H01L21/308 , H01L21/762
CPC分类号： H01L21/3085 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L2924/0002
摘要： A method and structure for forming a trench within a semiconductor layer (12) of material is provided. A first mask structure comprising a third insulating layer (20) and a fourth insulating layer (22) is formed adjacent a semiconductor layer (12). Sidewall spacers comprising a first and second portion (30) and (32) are formed along the sidewall (25) of layers (20) and (22) and extending outwardly the refrom. A second mask structure comprising a field insulating region (36) is formed adjacent first sidewall spacer portions (30) and along semiconductor layer (12). The foot portions (34) of first sidewall spacer portions (30) are removed thereby defining an exposed area (38) between the first mask structure and second mask structure. A trench (40) may then be formed between the two mask structures and filled with dielectrical material in order to isolate a semiconductor mesa (42) from semiconductor regions (44a) and 44b).
摘要翻译：提供了一种用于在半导体层（12）内形成沟槽的方法和结构。在半导体层（12）附近形成包括第三绝缘层（20）和第四绝缘层（22）的第一掩模结构。包括第一和第二部分（30）和（32）的侧壁间隔物沿着层（20）和（22）的侧壁（25）形成并向外延伸。包括场绝缘区域（36）的第二掩模结构邻近第一侧壁间隔部分（30）并且沿着半导体层（12）形成。去除第一侧壁间隔部分（30）的脚部（34），从而限定第一掩模结构和第二掩模结构之间的暴露区域（38）。然后可以在两个掩模结构之间形成沟槽（40），并且填充有介电材料，以便将半导体台面（42）与半导体区域（44a）和44b隔离开。

5. 发明授权

US4797373A Method of making dRAM cell with trench capacitor 失效
标题翻译：制造具有沟槽电容器的dRAM单元的方法
公开(公告)号：US4797373A
公开(公告)日：1989-01-10
申请号：US122560
申请日：1987-11-12
申请人： Satwinder S. Malhi , Gordon P. Pollack
发明人： Satwinder S. Malhi , Gordon P. Pollack
IPC分类号： H01L21/225 , H01L21/8242 , H01L27/108 , H01L27/10 , H01L21/302
CPC分类号： H01L27/10864 , H01L21/2257 , H01L27/10841
摘要： A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.
摘要翻译：公开了一种dRAM单元和单元阵列及其制造方法，其中单元包括一个场效应晶体管和一个存储电容器，晶体管和电容器都形成在衬底中的沟槽中。晶体管源极，沟道和漏极以及一个电容器板基本垂直地形成在沟槽的主体衬底侧壁中，并且栅极和其它电容器板形成在插入到沟槽中的两个材料区域中，并且通过绝缘体与本体隔离层。信号电荷通过绝缘层通过体衬底源与电容器材料的电连接而被存储在插入到沟槽中的电容器材料上。在优选实施例中，衬底表面上的字线连接到形成栅极的插入区域的上部，衬底表面上的位线形成漏极。在位线和字线的交叉处形成沟槽和电池; 位线和字线形成垂直的平行线组。

6. 发明授权

US5162882A Semiconductor over insulator mesa 失效
标题翻译：绝缘体半导体台面
公开(公告)号：US5162882A
公开(公告)日：1992-11-10
申请号：US697144
申请日：1991-05-08
申请人： Gordon P. Pollack
发明人： Gordon P. Pollack
IPC分类号： H01L21/20 , H01L21/311 , H01L21/336 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/31144 , H01L21/84 , Y10S257/90
摘要： An improved SOI structure 40 is provided. SOI structure 40 includes a semiconductor mesa 42 formed over a buried insulating layer 46 which overlies a substrate 48. Sidewall insulator regions 50 and 52 are formed along sidewalls 54 and 56, respectively, of semiconductor mesa 42. Sidewall spacers 62 and 64 are formed along sidewall insulator regions 50 and 52, respectively. Sidewall spacers 62 and 64 each include respective foot regions 66 and 68. Foot regions 66 and 68 effectively shift undercut areas 74 and 76 laterally away from semiconductor mesa 42.
摘要翻译：提供了改进的SOI结构40。 SOI结构40包括形成在覆盖衬底48的掩埋绝缘层46上的半导体台面42。侧壁绝缘体区域50和52分别沿着半导体台面42的侧壁54和56形成。侧壁间隔件62和64沿着侧壁绝缘体区域50和52。侧壁间隔件62和64各自包括相应的脚部区域66和68.脚部区域66和68有效地将底切区域74和76横向偏离半导体台面42。

7. 发明授权

US5039621A Semiconductor over insulator mesa and method of forming the same 失效
标题翻译：半导体绝缘子台面及其形成方法
公开(公告)号：US5039621A
公开(公告)日：1991-08-13
申请号：US534920
申请日：1990-06-08
申请人： Gordon P. Pollack
发明人： Gordon P. Pollack
IPC分类号： H01L21/20 , H01L21/311 , H01L21/336 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/31144 , H01L21/84 , Y10S257/90
摘要： An improved SOI structure 40 is provided. SOI structure 40 includes a semiconductor mesa 42 formed over a buried insulating layer 46 which overlies a substrate 48. Sidewall insulator regions 50 and 52 are formed along sidewalls 54 and 56, respectively, of semiconductor mesa 42. Sidewall spacers 62 and 64 are formed along sidewall insulator regions 50 and 52, respectively. Sidewall spacers 62 and 64 each include respective foot regions 66 and 68. Foot regions 66 and 68 effectively shift undercut areas 74 and 76 laterally away from semiconductor mesa 42.
摘要翻译：提供了改进的SOI结构40。 SOI结构40包括形成在覆盖衬底48的掩埋绝缘层46上的半导体台面42。侧壁绝缘体区域50和52分别沿着半导体台面42的侧壁54和56形成。侧壁间隔件62和64沿着侧壁绝缘体区域50和52。侧壁间隔件62和64各自包括相应的脚部区域66和68.脚部区域66和68有效地将底切区域74和76横向偏离半导体台面42。

8. 发明授权

US4659426A Plasma etching of refractory metals and their silicides 失效
$Plasma etching of refractory metals and their silicides$
标题翻译：难熔金属及其硅化物的等离子体蚀刻
公开(公告)号：US4659426A
公开(公告)日：1987-04-21
申请号：US730717
申请日：1985-05-03
申请人： Clyde R. Fuller , Gordon P. Pollack , Robert H. Eklund , Dave Monahan
发明人： Clyde R. Fuller , Gordon P. Pollack , Robert H. Eklund , Dave Monahan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/02
CPC分类号： H01L21/32136 , H01L21/32137
摘要： Refractory metals, refractory metal silicide, and polysilicon/refractory metal silicide sandwich structures integrated circuits are etched using carbonyl chemistry. That is, the deposited material is plasma etched using an etchant gas mixture which contains a gas, such as CO2, which can dissociate to provide carbonyl groups (CO) or, in combination with halogen sources, carbonyl halide radicals.
摘要翻译：耐火金属，难熔金属硅化物和多晶硅/耐火金属硅化物夹层结构集成电路使用羰基化学蚀刻。也就是说，沉积的材料是使用含有诸如CO 2的气体的蚀刻剂气体混合物进行等离子体蚀刻，其可以离解以提供羰基（CO）或与卤素源组合形成羰基卤基团。

9. 发明授权

US5185280A Method of fabricating a SOI transistor with pocket implant and body-to-source (BTS) contact 失效
标题翻译：制造具有袋状植入物和体内源（BTS）接触的SOI晶体管的方法
公开(公告)号：US5185280A
公开(公告)日：1993-02-09
申请号：US647111
申请日：1991-01-29
申请人： Theodore W. Houston , Gordon P. Pollack
发明人： Theodore W. Houston , Gordon P. Pollack
IPC分类号： H01L21/22 , H01L21/336 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/78612
摘要： A silicon-on-insulator MOS transistor is disclosed that has an implanted region of the same conductivity type as the body underneath one or both of the extended drain and source portoins of the drain and the source with and without a BTS contact or a general body contact. With only the pocket implants, the back gate threshold voltage is enhanced to reduce the possibility of back gate current flowing. With the pocket implants and a body contact, the floating body effects are minimized. Due to the BTS contact being located as far into the source as the pocket implant extends, negligible impact is made on the device channel. Ohmic connection between the source and the body is made for example by way of silicidation.

10. 发明授权

US4538343A Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking 失效
标题翻译：通道停止隔离技术利用两步蚀刻和选择性氧化与侧壁掩蔽
公开(公告)号：US4538343A
公开(公告)日：1985-09-03
申请号：US620995
申请日：1984-06-15
申请人： Gordon P. Pollack , Clarence Teng , William R. Hunter
发明人： Gordon P. Pollack , Clarence Teng , William R. Hunter
IPC分类号： H01L29/78 , H01L21/76 , H01L21/762 , H01L29/06 , H01L21/31
CPC分类号： H01L29/0638 , H01L21/76232 , H01L21/76237 , Y10S148/085 , Y10S148/117
摘要： A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon etch. The first channel stop implant is performed after the first silicon etch, before the sidewall nitride is deposited. A further silicon etch is performed after the sidewall nitride is in place, and a second channel stop implant follows. The first implant can be a light dose, to avoid excess subthreshold leakage in the active devices due to field-assisted turn on at the corners of the moat regions, and the second implant can be a very heavy dose to provide complete isolation without any danger of the channel stop species encroaching on the active device regions.
摘要翻译：通过执行两步硅蚀刻，侧壁氮化物隔离技术避免了应力引起的缺陷，同时允许重通道停止注入以避免场氧化物晶体管的导通。在第一硅蚀刻之后，在侧壁氮化物沉积之前执行第一通道停止注入。在侧壁氮化物就位之后进行另外的硅蚀刻，并且跟随第二通道停止注入。第一种植入物可以是轻剂量，以避免由于在护环区域的角落处的场辅助打开而导致的活动装置中的过度亚阈值泄漏，并且第二种植入物可以是非常重的剂量以提供完全隔离而没有任何危险的通道停止物种侵入有源器件区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式