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1. 发明授权

US4978634A Method of making trench DRAM cell with stacked capacitor and buried lateral contact 失效
标题翻译：制造具有堆叠电容器和埋入侧面接触的沟槽DRAM单元的方法
公开(公告)号：US4978634A
公开(公告)日：1990-12-18
申请号：US385327
申请日：1989-07-25
申请人： Bing-Whey Shen , Masaaki Yashiro , Randy McKee , Gishi Chung , Kiyoshi Shirai , Clarence Teng , Donald J. Coleman, Jr.
发明人： Bing-Whey Shen , Masaaki Yashiro , Randy McKee , Gishi Chung , Kiyoshi Shirai , Clarence Teng , Donald J. Coleman, Jr.
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861
摘要： The described embodiments of the present invention provide DRAM cells, structures and manufaturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit. The use of a self-aligned bitline contact between two memory cells allows for the elimination of alignment tolerances between the bitline contact and the gates of the transfer transistors of the memory cells.
摘要翻译：本发明的所述实施例提供了DRAM单元，结构和制造方法。在第一实施例中，制造具有沟槽电容器的DRAM单元，该沟槽电容器具有形成为在衬底中形成的沟槽的外表面上的扩散的第一板，以及形成在沟槽内部的导电区域的第二板。转移晶体管使用场板隔离结构形成，该场板隔离结构包括用于转移晶体管的自对准的沟槽区域。护城河区域与电容器区域稍微重叠，并且允许增加的不对准公差，从而对DRAM单元的布局中内置的未对准公差的要求进行了前提。场板本身被蚀刻，使得其具有倾斜的侧壁，以避免由形成在集成电路上的后续导电层形成导电细丝。使用两个存储单元之间的自对准位线接触允许消除位线接触和存储器单元的传输晶体管的栅极之间的对准公差。

2. 发明授权

US5111259A Trench capacitor memory cell with curved capacitors 失效
标题翻译：具有弯曲电容器的沟槽电容器存储单元
公开(公告)号：US5111259A
公开(公告)日：1992-05-05
申请号：US385340
申请日：1989-07-25
申请人： Clarence Teng , Peter Ying
发明人： Clarence Teng , Peter Ying
IPC分类号： H01L21/311 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L21/31116 , H01L27/10829
摘要： The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. In another embodiment of the present invention, a planar capacitor is used with a field plate isolation scheme including a transfer transistor moat region self-aligned to the field plate. This structure allows the elimination of alignment tolerances between the capacitor and the transistor thus reducing the space necessary between the transistor and the capacitor.In another embodiment of the present invention, a memory cell using two conductive plates formed inside a trench as the storage capacitor is fabricated. A field plate isolation scheme which allows for self-alignment of the moat containing the transfer transistor is used thus allowing for self-alignment of the moat and elimination of alignment tolerances between the moat region and the source drain diffusions. In addition, a sidewall insulator technique using two different materials, which may be selectively etched between one another, is used.
摘要翻译：本发明的所述实施例提供了DRAM单元，结构和制造方法。在第一实施例中，制造具有沟槽电容器的DRAM单元，该沟槽电容器具有形成为在衬底中形成的沟槽的外表面上的扩散的第一板，以及形成在沟槽内部的导电区域的第二板。在本发明的另一个实施例中，平面电容器被用于场板隔离方案，包括与场板板自对准的转移晶体管护壕区域。该结构允许消除电容器和晶体管之间的对准公差，从而减小晶体管和电容器之间所需的空间。在本发明的另一实施例中，制造了使用形成在沟槽内的两个导电板作为存储电容器的存储单元。因此，使用允许包含转移晶体管的护城河的自对准的场板隔离方案，因此允许护城河的自对准以及消除护壕区域和源极漏极扩散之间的对准公差。此外，使用使用可以彼此间选择性蚀刻的两种不同材料的侧壁绝缘体技术。

3. 发明授权

US4538343A Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking 失效
标题翻译：通道停止隔离技术利用两步蚀刻和选择性氧化与侧壁掩蔽
公开(公告)号：US4538343A
公开(公告)日：1985-09-03
申请号：US620995
申请日：1984-06-15
申请人： Gordon P. Pollack , Clarence Teng , William R. Hunter
发明人： Gordon P. Pollack , Clarence Teng , William R. Hunter
IPC分类号： H01L29/78 , H01L21/76 , H01L21/762 , H01L29/06 , H01L21/31
CPC分类号： H01L29/0638 , H01L21/76232 , H01L21/76237 , Y10S148/085 , Y10S148/117
摘要： A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon etch. The first channel stop implant is performed after the first silicon etch, before the sidewall nitride is deposited. A further silicon etch is performed after the sidewall nitride is in place, and a second channel stop implant follows. The first implant can be a light dose, to avoid excess subthreshold leakage in the active devices due to field-assisted turn on at the corners of the moat regions, and the second implant can be a very heavy dose to provide complete isolation without any danger of the channel stop species encroaching on the active device regions.
摘要翻译：通过执行两步硅蚀刻，侧壁氮化物隔离技术避免了应力引起的缺陷，同时允许重通道停止注入以避免场氧化物晶体管的导通。在第一硅蚀刻之后，在侧壁氮化物沉积之前执行第一通道停止注入。在侧壁氮化物就位之后进行另外的硅蚀刻，并且跟随第二通道停止注入。第一种植入物可以是轻剂量，以避免由于在护环区域的角落处的场辅助打开而导致的活动装置中的过度亚阈值泄漏，并且第二种植入物可以是非常重的剂量以提供完全隔离而没有任何危险的通道停止物种侵入有源器件区域。

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