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1. 发明授权

US4956307A Thin oxide sidewall insulators for silicon-over-insulator transistors 失效
标题翻译：用于硅绝缘体晶体管的薄氧化物侧壁绝缘体
公开(公告)号：US4956307A
公开(公告)日：1990-09-11
申请号：US269803
申请日：1988-11-10
申请人： Gordon P. Pollack , Mishel Matloubian , Ravishankar Sundaresan
发明人： Gordon P. Pollack , Mishel Matloubian , Ravishankar Sundaresan
IPC分类号： G21F1/08 , H01L21/321 , H01L21/336 , H01L27/12 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/32105 , H01L29/4908 , Y10S257/906 , Y10S438/911 , Y10S438/953
摘要： A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa's insulating region (46). This oxidizable layer (56) is then anisotropically etched, resulting in oxidizable sidewalls (60). An optional foot (70) may be formed at the bottom edge of the oxidizable sidewalls (76). These oxidizable sidewalls (76) are then oxidized, resulting in a pure oxide sidewall (64). The gate (66) is then formed over the pure oxide sidewalls (64) and a gate oxide (62).
摘要翻译：提供了具有覆盖掩埋氧化物（42）的半导体台面（40）的绝缘体上硅晶体管。绝缘区域（50）形成在半导体台面（40）的侧面。在台面绝缘区域（46）之上形成可氧化层（56）。然后对该可氧化层（56）进行各向异性蚀刻，得到可氧化的侧壁（60）。可选的脚（70）可以形成在可氧化侧壁（76）的底部边缘处。然后，这些可氧化的侧壁（76）被氧化，产生纯氧化物侧壁（64）。然后，在纯氧化物侧壁（64）和栅极氧化物（62）上形成栅极（66）。

2. 发明授权

US4950618A Masking scheme for silicon dioxide mesa formation 失效
标题翻译：二氧化硅台面形成掩蔽方案
公开(公告)号：US4950618A
公开(公告)日：1990-08-21
申请号：US338719
申请日：1989-04-14
申请人： Ravishankar Sundaresan , Mishel Matloubian
发明人： Ravishankar Sundaresan , Mishel Matloubian
IPC分类号： H01L21/033 , H01L21/266
CPC分类号： H01L21/266 , H01L21/033 , Y10S148/053 , Y10S148/082
摘要： An improved masking stack (63) comprises a pad oxide (58), polysilicon (60) and nitride (62). After forming a photoresist pattern (64) over the stack (63), an anisotropic etch is performed to remove the nitride (62) and a portion of the polysilicon (60) not covered by the pattern (64). Another etch is performed to remove the remaining polysilicon (60) to leave at least a portion of the pad oxide (58). A boron implant (66) is conducted to form implant areas (68 and 70) within the unmasked silicon active device layer (56). A portion of the implant areas (68 and 70) is masked with nitride (72), and the unmasked silicon layer (56) is then etched. The masking stack (63) and the nitride (72) is removed and unprotected silicon layer (56) and implant areas (68 and 70) are covered with an oxide forming the silicon dioxide mesa (78).
摘要翻译：改进的掩模叠层（63）包括衬垫氧化物（58），多晶硅（60）和氮化物（62）。在堆叠（63）上形成光致抗蚀剂图案（64）之后，进行各向异性蚀刻以除去未被图案（64）覆盖的氮化物（62）和多晶硅（60）的一部分。执行另一蚀刻以去除剩余的多晶硅（60）以留下衬垫氧化物（58）的至少一部分。导电硼植入物（66）在未掩模的硅有源器件层（56）内形成植入区域（68和70）。植入区域（68和70）的一部分用氮化物（72）掩蔽，然后对未掩模的硅层（56）进行蚀刻。除去掩蔽堆叠（63）和氮化物（72），并且用形成二氧化硅台面（78）的氧化物覆盖未保护的硅层（56）和植入区域（68和70）。

3. 发明授权

US06812142B1 Method and interlevel dielectric structure for improved metal step coverage 失效
标题翻译：方法和层间电介质结构，改善金属台阶覆盖
公开(公告)号：US06812142B1
公开(公告)日：2004-11-02
申请号：US09712827
申请日：2000-11-14
申请人： Loi Nguyen , Ravishankar Sundaresan
发明人： Loi Nguyen , Ravishankar Sundaresan
IPC分类号： H01L214763
CPC分类号： H01L21/76804 , H01L21/76801 , H01L21/76829
摘要： A VLSI contact formation process in which a nitride layer is used to stop a wet oxide etch. An anisotropic plasma etch is used to cut a substantially vertical contact hole through the nitride and underlying layers. Thus, the resulting contact hole has a “Y”-shaped profile.
摘要翻译：使用氮化物层来阻止湿氧化物蚀刻的VLSI接触形成工艺。使用各向异性等离子体蚀刻来切割穿过氮化物层和下层的基本垂直的接触孔。因此，所得到的接触孔具有“Y”形轮廓。

4. 发明授权

US5723988A CMOS with parasitic bipolar transistor 失效
标题翻译： CMOS与寄生双极晶体管
公开(公告)号：US5723988A
公开(公告)日：1998-03-03
申请号：US139490
申请日：1993-10-20
申请人： Shivaling S. Mahant-Shetti , Mark G. Harward , Lawrence A. Arledge, Jr. , Ravishankar Sundaresan
发明人： Shivaling S. Mahant-Shetti , Mark G. Harward , Lawrence A. Arledge, Jr. , Ravishankar Sundaresan
IPC分类号： H01L27/06 , H03K17/567 , H03K19/08 , H03K19/0948
CPC分类号： H01L27/0623 , H03K17/567
摘要： A device is disclosed which combines the advantages of CMOS and bipolar using an existing parasitic bipolar device. As such high on-chip density is attainable with the device along with high speed capability while maintaining low power advantages.
摘要翻译：公开了一种使用现有的寄生双极器件结合CMOS和双极的优点的器件。由于器件同时具有高速能力同时保持低功率优点，所以可实现高的片上密度。

5. 发明授权

US5710461A SRAM cell fabrication with interlevel dielectric planarization 失效
公开(公告)号：US5710461A
公开(公告)日：1998-01-20
申请号：US781429
申请日：1997-01-10
申请人： Loi Nguyen , Ravishankar Sundaresan
发明人： Loi Nguyen , Ravishankar Sundaresan
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/8244 , H01L29/34 , H01L23/48 , H01L23/522 , H01L29/54
CPC分类号： H01L21/76819 , H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

6. 发明授权

US5298782A Stacked CMOS SRAM cell with polysilicon transistor load 失效
标题翻译：堆叠CMOS SRAM单元与多晶硅晶体管负载
公开(公告)号：US5298782A
公开(公告)日：1994-03-29
申请号：US709634
申请日：1991-06-03
申请人： Ravishankar Sundaresan
发明人： Ravishankar Sundaresan
IPC分类号： H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L27/01 , H01L21/265
CPC分类号： H01L27/1108
摘要： A CMOS SRAM memory cell, and a method of making the same, is disclosed. The disclosed cell is configured as cross-coupled CMOS inverters, with the n-channel pull-down transistors in bulk, and with the p-channel load devices being accumulation mode p-channel transistors in a thin polysilicon film. The cross-coupling connection is made by way of an intermediate layer, which may include polysilicon at its top surface for performance enhancement, each of which makes contact to the drain region of an n-channel transistor, and to the opposite gate electrode, via a buried contact. The intermediate layer also serves as the gate for the thin-film p-channel transistor, which has its channel region overlying the intermediate layer. The p-channel transistors may be formed so as to overlie part of the n-channel transistor in its inverter, thus reducing active chip area required for implementation of the memory cell.
摘要翻译：公开了一种CMOS SRAM存储单元及其制造方法。所公开的单元被配置为交叉耦合CMOS反相器，其中n沟道下拉晶体管是本体，并且p沟道负载器件是在多晶硅薄膜中的堆积模式p沟道晶体管。交叉耦合连接是通过中间层进行的，中间层可以在其顶表面包括用于性能增强的多晶硅，其中每一个都与n沟道晶体管的漏极区域接触，并且通过埋葬的联系人。中间层还用作薄膜p沟道晶体管的栅极，其具有覆盖中间层的沟道区。 p沟道晶体管可以形成为覆盖其逆变器中的n沟道晶体管的一部分，从而减少了实现存储单元所需的有效芯片面积。

7. 发明授权

US4628589A Method for fabricating stacked CMOS structures 失效
标题翻译：堆叠CMOS结构的制造方法
公开(公告)号：US4628589A
公开(公告)日：1986-12-16
申请号：US656056
申请日：1984-09-28
申请人： Ravishankar Sundaresan
发明人： Ravishankar Sundaresan
IPC分类号： H01L27/00 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/78 , H01L29/786 , H01L21/385
CPC分类号： H01L21/8221
摘要： In stacked CMOS, a single gate in first level polysilicon is used to address both an n-channel device in the substrate and an overlayed p-channel device. To self-align the p-channel polycrystalline silicon device to the gate, a layer of polycrystalline silicon is deposited over the integrated circuit, followed by spinning on a layer of doped oxide which is then etched back to expose the polycrystalline silicon over the gate region. Thermally annealing the integrated circuit causes dopant from the doped layer to diffuse into the polycrystalline layer, thereby forming self-aligned source and drain structures.
摘要翻译：在堆叠CMOS中，使用第一级多晶硅中的单个栅极来寻址衬底中的n沟道器件和覆盖的p沟道器件。为了将p沟道多晶硅器件自对准到栅极，在集成电路上沉积多晶硅层，随后在掺杂氧化物层上旋转，然后将其回蚀刻以在栅极区域上暴露多晶硅。集成电路的热退火使得掺杂剂掺杂剂扩散到多晶层中，从而形成自对准的源极和漏极结构。

8. 发明授权

US06753576B1 Method of fabricating a one-sided polysilicon thin film transistor 失效
标题翻译：制造单面多晶硅薄膜晶体管的方法
公开(公告)号：US06753576B1
公开(公告)日：2004-06-22
申请号：US08193725
申请日：1994-02-09
申请人： Ravishankar Sundaresan
发明人： Ravishankar Sundaresan
IPC分类号： H01L2976
CPC分类号： H01L29/66765 , H01L29/78624
摘要： An asymmetrical polysilicon thin film transistor is formed above a gate electrode on a semiconductor substrate. The transistor is separated from the gate electrode by a gate oxide layer, and includes a channel region immediately above the gate electrode. Highly doped source/drain regions are formed within the polysilicon on either side of the channel region. On the drain side of the channel only, a lightly doped drain region is formed between the channel region and the highly doped drain region. The highly doped source region is immediately adjacent the channel region.
摘要翻译：在半导体衬底上的栅电极上方形成非对称多晶硅薄膜晶体管。晶体管通过栅极氧化层与栅电极分离，并且包括在栅电极正上方的沟道区。在沟道区两侧的多晶硅内形成高掺杂源/漏区。仅在沟道的漏极侧，在沟道区和高掺杂漏极区之间形成轻掺杂漏极区。高度掺杂的源极区域紧邻沟道区域。

9. 发明授权

US06566209B2 Method to form shallow junction transistors while eliminating shorts due to junction spiking 失效
公开(公告)号：US06566209B2
公开(公告)日：2003-05-20
申请号：US09943307
申请日：2001-08-31
申请人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
发明人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/28044 , H01L29/41775 , H01L29/41783 , H01L29/456 , H01L29/4916 , H01L29/4941 , H01L29/665 , H01L29/66545
摘要： A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions. The second electrode layer is etched through to form separate conductive connections. An intermetal dielectric layer is deposited. The intermetal dielectric layer is etched through to form contact openings. A metal layer is deposited and etched through to form separate metal interconnects. A passivation layer is deposited, and the integrated circuit is completed.

10. 发明授权

US6107642A SRAM cell with thin film transistor using two polysilicon layers 失效
标题翻译：具有薄膜晶体管的SRAM单元使用两个多晶硅层
公开(公告)号：US6107642A
公开(公告)日：2000-08-22
申请号：US899670
申请日：1997-07-24
申请人： Ravishankar Sundaresan
发明人： Ravishankar Sundaresan
IPC分类号： H01L21/311 , H01L27/108
CPC分类号： H01L21/31111
摘要： A TFT formed on a semiconductor substrate of a first conductivity type, includes a first doped portion of a polysilicon layer over FOX regions and a first insulating layer. A buried contact extends through the first portion of a polysilicon layer and the first insulating layer to the surface of the substrate adjacent to a FOX region. A second doped portion of the polysilicon layer overlies the first portion and forms a buried contact between the second portion and the substrate. The polysilicon layer forms a gate electrode and a conductor from the buried contact. Doped source/drain regions in the substrate are juxtaposed with the gate electrode. An interelectrode dielectric layer over the gate electrode and the conductor has a gate opening therethrough down to the substrate. A gate oxide layer is formed on the surface of the substrate at the gate opening. A semiconductor film extends over the interelectrode dielectric layer and over the surface of the substrate through the gate opening. A doped channel region is formed between source/drain regions in the semiconductor film above the gate opening, and above the gate opening of a TFT, with the doped region therebelow comprising the gate of the TFT.
摘要翻译：形成在第一导电类型的半导体衬底上的TFT包括在FOX区域上的多晶硅层的第一掺杂部分和第一绝缘层。埋入的触点延伸穿过多晶硅层的第一部分，并且第一绝缘层延伸到与FOX区域相邻的衬底的表面。多晶硅层的第二掺杂部分覆盖第一部分，并在第二部分和衬底之间形成掩埋接触。多晶硅层从掩埋触点形成栅电极和导体。衬底中的掺杂源极/漏极区域与栅电极并置。栅电极和导体之间的电极间电介质层具有通向其中的基板的栅极开口。栅极氧化层在栅极开口处形成在衬底的表面上。半导体膜通过栅极开口在电极之间的电介质层上延伸到衬底的表面上方。掺杂沟道区形成在栅极开口上方的半导体膜的源极/漏极区域之间以及TFT的栅极开口的上方，其中掺杂区域包括TFT的栅极。

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