专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06847089B2 Gate edge diode leakage reduction 有权
标题翻译：栅极二极管漏电减少
公开(公告)号：US06847089B2
公开(公告)日：2005-01-25
申请号：US10407128
申请日：2003-04-03
申请人： Srinivasan Chakravarthi , Suresh Potla , Gordon P. Pollack , Amitabh Jain
发明人： Srinivasan Chakravarthi , Suresh Potla , Gordon P. Pollack , Amitabh Jain
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6656
摘要： An embodiment of the invention is an integrated circuit 2 having halo atoms 12 concentrated at a gate side of a channel region and impurity atoms 14 within the channel region. Another embodiment of the invention is a method of manufacturing an integrated circuit that includes the implantation of impurity atoms 14 into a semiconductor substrate 11.
摘要翻译：本发明的一个实施例是集成电路2，其具有集中在沟道区的栅极侧的光子原子12和沟道区内的杂质原子14。本发明的另一实施例是一种制造集成电路的方法，该集成电路包括将杂质原子14注入到半导体衬底11中。

2. 发明授权

US5482871A Method for forming a mesa-isolated SOI transistor having a split-process polysilicon gate 失效
标题翻译：用于形成具有分裂工艺多晶硅栅极的台面隔离SOI晶体管的方法
公开(公告)号：US5482871A
公开(公告)日：1996-01-09
申请号：US228043
申请日：1994-04-15
申请人： Gordon P. Pollack
发明人： Gordon P. Pollack
IPC分类号： H01L21/02 , H01L21/265 , H01L21/336 , H01L27/12 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/78609 , H01L29/78621
摘要： A method for forming a mesa-isolated SOI transistor using a split-process polysilicon gate including the steps of depositing a layer of buried oxide (14) on a silicon substrate (12), depositing an SOI layer (16) on buried oxide layer (14), and forming a gate oxide layer (18) on the SOI layer (16). Further steps are to form a gate polysilicon mesa (20) on the gate oxide layer, and an SOI mesa (28) on gate polysilicon mesa (20) and forming an oxide sidewall (26) on the gate polysilicon mesa (20) and SOI mesa (28). A gate electrode (38) is the formed along with an oxide sidewall (36). Implanting gate electrode (38) with a boron implant occurs next, after which an oxide sidewall is formed on the gate electrode (38). The gate electrode (38) is implanted with phosphorus to form source and drain region. Thereafter annealing the structure takes place.
摘要翻译：一种使用分割工艺多晶硅栅极形成台面隔离SOI晶体管的方法，包括以下步骤：在硅衬底（12）上沉积一层掩埋氧化物（14），在掩埋氧化物层上沉积SOI层（16） 14），并在SOI层（16）上形成栅氧化层（18）。进一步的步骤是在栅极氧化物层上形成栅极多晶硅台面（20），在栅极多晶硅台面（20）上形成SOI台面（28），并在栅极多晶硅台面（20）和SOI上形成氧化物侧壁（26）台面（28）。栅电极（38）与氧化物侧壁（36）一起形成。随后将硼注入物注入栅电极（38），之后在栅电极（38）上形成氧化物侧壁。栅电极（38）注入磷以形成源区和漏区。此后进行结构退火。

3. 发明授权

US5225697A dRAM cell and method 失效
标题翻译： dRAM单元格和方法
公开(公告)号：US5225697A
公开(公告)日：1993-07-06
申请号：US859286
申请日：1992-03-26
申请人： Satwinder S. Malhi , Gordon P. Pollack , William F. Richardson
发明人： Satwinder S. Malhi , Gordon P. Pollack , William F. Richardson
IPC分类号： H01L21/225 , H01L21/334 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L21/2257 , H01L27/10841 , H01L29/66181
摘要： A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.
摘要翻译：公开了一种dRAM单元和单元阵列及其制造方法，其中单元包括一个场效应晶体管和一个存储电容器，晶体管和电容器都形成在衬底中的沟槽中。晶体管源极，沟道和漏极以及一个电容器板基本垂直地形成在沟槽的主体衬底侧壁中，并且栅极和其它电容器板形成在插入到沟槽中的两个材料区域中，并且通过绝缘体与本体隔离层。信号电荷通过绝缘层通过体衬底源与电容器材料的电连接而被存储在插入到沟槽中的电容器材料上。在优选实施例中，衬底表面上的字线连接到形成栅极的插入区域的上部，并且衬底表面上的位线形成漏极。在位线和字线的交叉处形成沟槽和电池; 位线和字线形成垂直的平行线组。

4. 发明授权

US4939104A Method for forming a buried lateral contact 失效
标题翻译：形成埋入侧面接触的方法
公开(公告)号：US4939104A
公开(公告)日：1990-07-03
申请号：US122604
申请日：1987-11-17
申请人： Gordon P. Pollack , Donald M. Bordelon , William F. Richardson , Satwinder S. Malhi
发明人： Gordon P. Pollack , Donald M. Bordelon , William F. Richardson , Satwinder S. Malhi
IPC分类号： H01L21/225 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L21/2257 , H01L27/10841
摘要： The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells.One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate, which is provided by the described embodiment of the invention.Another embodiment of the present invention is an interconnection between a surface conductor and the surface of the substrate. This embodiment uses a conductive plug formed between the conductor and the substrate to form an interconnection using a minimum of surface area of the substrate.
摘要翻译：结合本发明的重要应用的dRAM单元的制造来描述本发明。所描述的单元提供单晶体管/单电容器dRAM单元结构和阵列，其中单元晶体管形成在包含单元电容器的基板沟槽的侧壁上; 字和位线跨过这个沟槽。晶体管在电容器顶部的堆叠产生在衬底上具有最小面积的电池，并解决了电池致密堆积的问题。一个电容器板和晶体管沟道和源极区域形成在沟槽的体侧壁中，并且晶体管栅极和电容器的另一个板都形成在沟槽中的多晶硅中，但是通过沟槽内的氧化物层彼此分离。信号电荷通过源区域与多晶硅电容器板的电连接而存储在多晶硅电容器板上，该多晶硅电容器板由本发明的所描述的实施例提供。本发明的另一实施例是表面导体与基片表面之间的互连。该实施例使用形成在导体和基板之间的导电插塞，以使用基板的最小表面积形成互连。

5. 发明授权

US4541167A Method for integrated circuit device isolation 失效
标题翻译：集成电路器件隔离方法
公开(公告)号：US4541167A
公开(公告)日：1985-09-17
申请号：US570145
申请日：1984-01-12
申请人： Robert H. Havemann , Gordon P. Pollack
发明人： Robert H. Havemann , Gordon P. Pollack
IPC分类号： H01L21/033 , H01L21/762 , H01L21/76
CPC分类号： H01L21/033 , H01L21/76216 , Y10S148/05
摘要： The disclosure relates to a method manufacturing semiconductor devices which minimizes encroachment by utilizing a polycrystalline silicon (polysilicon) layer over a grown oxide on the substrate with a nitride layer positioned above the polysilicon layer. A patterned resist is then formed in the active device regions and the device is then etched in the regions where the resist has not been applied to remove the nitride layer, the polysilicon layer and the oxide layer in one embodiment and, in a second embodiment, also removes a portion of the substrate. The silicon substrate portion which is exposed is then oxidized by field oxidation to provide, in the first embodiment, an oxide layer which rises above the level of the polysilicon layer and, in the second embodiment, to a point equal to or slightly above the oxide layer beneath the polysilicon layer. The nitride and polysilicon layer are then stripped or, alternatively, the polysilicon layer can be oxidized. The oxide layer in the active region is then etched back to the silicon layer and a gate oxide is then formed in the active region in standard manner. The processing then continues in standard manner to provide an MOS or bipolar device. The above noted procedure provides active semiconductor devices with essentially no encroachment or "bird beak" problem present. The procedure can also be used with elimination of the first oxide layer over the substrate.
摘要翻译：本公开涉及一种制造半导体器件的方法，其通过在衬底上的生长的氧化物上利用多晶硅（多晶硅）层来最小化侵入，其中位于多晶硅层上方的氮化物层。然后在有源器件区域中形成图案化的抗蚀剂，然后在一个实施例中，在没有施加抗蚀剂的区域中蚀刻器件以去除氮化物层，多晶硅层和氧化物层，并且在第二实施例中，也去除了衬底的一部分。暴露的硅衬底部分然后通过场氧化来氧化，以在第一实施例中提供一个氧化物层，其上升到多晶硅层的高度以上，并且在第二实施例中提供到等于或略高于氧化物的点多晶硅层下面。然后将氮化物和多晶硅层剥离，或者，多晶硅层可被氧化。然后将有源区中的氧化物层回蚀刻到硅层，然后以标准方式在有源区中形成栅极氧化物。然后以标准方式继续处理以提供MOS或双极器件。上述步骤提供了基本上没有侵入或“鸟嘴”问题存在的有源半导体器件。该方法也可用于消除衬底上的第一氧化物层。

6. 发明授权

US5120675A Method for forming a trench within a semiconductor layer of material 失效
标题翻译：在材料的半导体层内形成沟槽的方法
公开(公告)号：US5120675A
公开(公告)日：1992-06-09
申请号：US531997
申请日：1990-06-01
申请人： Gordon P. Pollack
发明人： Gordon P. Pollack
IPC分类号： H01L21/308 , H01L21/762
CPC分类号： H01L21/76264 , H01L21/3085 , H01L21/76281 , H01L21/76283
摘要： A method and structure for forming a trench within a semiconductor layer (12) of material is provided. A first mask structure comprising a third insulating layer (20) and a fourth insulating layer (22) is formed adjacent a semiconductor layer (12). Sidewall spacers comprising a first and second portion (30) and (32) are formed along the sidewall (25) of layers (20) and (22) and extending outwardly therefrom. A second mask structure comprising a field insulating region (36) is formed adjacent first sidewall spacer portions (30) and along semicondcutor layer (12). The foot portions (34) of first sidewall spacer portions (30) are removed thereby defining an exposed area (38) between the first mask structure and second mask structure. A trench (40) may then be formed between the two mask structures and filled with dielectrical material in order to isolate a semiconductor mesa (42) from semiconductor regions (44a) and 44b).
摘要翻译：提供了一种用于在半导体层（12）内形成沟槽的方法和结构。在半导体层（12）附近形成包括第三绝缘层（20）和第四绝缘层（22）的第一掩模结构。包括第一和第二部分（30）和（32）的侧壁间隔物沿着层（20）和（22）的侧壁（25）形成并从其向外延伸。包括场绝缘区域（36）的第二掩模结构邻近第一侧壁间隔部分（30）并且沿半切割层（12）形成。去除第一侧壁间隔部分（30）的脚部（34），从而限定第一掩模结构和第二掩模结构之间的暴露区域（38）。然后可以在两个掩模结构之间形成沟槽（40），并且填充有介电材料，以便将半导体台面（42）与半导体区域（44a）和44b隔离开。

7. 发明授权

US4580330A Integrated circuit isolation 失效
标题翻译：集成电路隔离
公开(公告)号：US4580330A
公开(公告)日：1986-04-08
申请号：US621019
申请日：1984-06-15
申请人： Gordon P. Pollack , Clarence W. Teng , William R. Hunter , Christopher Slawinski , Robert R. Doering
发明人： Gordon P. Pollack , Clarence W. Teng , William R. Hunter , Christopher Slawinski , Robert R. Doering
IPC分类号： H01L29/78 , H01L21/32 , H01L21/76 , H01L21/762 , H01L29/06
CPC分类号： H01L29/0638 , H01L21/32 , H01L21/76232 , Y10S148/05
摘要： An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.
摘要翻译：一种集成电路隔离技术，其中通过在将第二氮化物（防止侵入的侧壁氮化物）添加到第一氮化物（覆盖护城河区域）之前执行底切和回填来改进现有技术的氮化物 - 侧壁方法。因此，使两个氮化物之间的对接更牢固，并且不会发生在护环氮化物和侧壁氮化物之间的对接接合处的局部鸟鸣。

8. 发明授权

US5240512A Method and structure for forming a trench within a semiconductor layer of material 失效
标题翻译：在材料的半导体层内形成沟槽的方法和结构
公开(公告)号：US5240512A
公开(公告)日：1993-08-31
申请号：US857041
申请日：1992-03-24
申请人： Gordon P. Pollack
发明人： Gordon P. Pollack
IPC分类号： H01L21/308 , H01L21/762
CPC分类号： H01L21/3085 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L2924/0002
摘要： A method and structure for forming a trench within a semiconductor layer (12) of material is provided. A first mask structure comprising a third insulating layer (20) and a fourth insulating layer (22) is formed adjacent a semiconductor layer (12). Sidewall spacers comprising a first and second portion (30) and (32) are formed along the sidewall (25) of layers (20) and (22) and extending outwardly the refrom. A second mask structure comprising a field insulating region (36) is formed adjacent first sidewall spacer portions (30) and along semiconductor layer (12). The foot portions (34) of first sidewall spacer portions (30) are removed thereby defining an exposed area (38) between the first mask structure and second mask structure. A trench (40) may then be formed between the two mask structures and filled with dielectrical material in order to isolate a semiconductor mesa (42) from semiconductor regions (44a) and 44b).
摘要翻译：提供了一种用于在半导体层（12）内形成沟槽的方法和结构。在半导体层（12）附近形成包括第三绝缘层（20）和第四绝缘层（22）的第一掩模结构。包括第一和第二部分（30）和（32）的侧壁间隔物沿着层（20）和（22）的侧壁（25）形成并向外延伸。包括场绝缘区域（36）的第二掩模结构邻近第一侧壁间隔部分（30）并且沿着半导体层（12）形成。去除第一侧壁间隔部分（30）的脚部（34），从而限定第一掩模结构和第二掩模结构之间的暴露区域（38）。然后可以在两个掩模结构之间形成沟槽（40），并且填充有介电材料，以便将半导体台面（42）与半导体区域（44a）和44b隔离开。

9. 发明授权

US4797373A Method of making dRAM cell with trench capacitor 失效
标题翻译：制造具有沟槽电容器的dRAM单元的方法
公开(公告)号：US4797373A
公开(公告)日：1989-01-10
申请号：US122560
申请日：1987-11-12
申请人： Satwinder S. Malhi , Gordon P. Pollack
发明人： Satwinder S. Malhi , Gordon P. Pollack
IPC分类号： H01L21/225 , H01L21/8242 , H01L27/108 , H01L27/10 , H01L21/302
CPC分类号： H01L27/10864 , H01L21/2257 , H01L27/10841
摘要： A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.
摘要翻译：公开了一种dRAM单元和单元阵列及其制造方法，其中单元包括一个场效应晶体管和一个存储电容器，晶体管和电容器都形成在衬底中的沟槽中。晶体管源极，沟道和漏极以及一个电容器板基本垂直地形成在沟槽的主体衬底侧壁中，并且栅极和其它电容器板形成在插入到沟槽中的两个材料区域中，并且通过绝缘体与本体隔离层。信号电荷通过绝缘层通过体衬底源与电容器材料的电连接而被存储在插入到沟槽中的电容器材料上。在优选实施例中，衬底表面上的字线连接到形成栅极的插入区域的上部，衬底表面上的位线形成漏极。在位线和字线的交叉处形成沟槽和电池; 位线和字线形成垂直的平行线组。

10. 发明授权

US5162882A Semiconductor over insulator mesa 失效
标题翻译：绝缘体半导体台面
公开(公告)号：US5162882A
公开(公告)日：1992-11-10
申请号：US697144
申请日：1991-05-08
申请人： Gordon P. Pollack
发明人： Gordon P. Pollack
IPC分类号： H01L21/20 , H01L21/311 , H01L21/336 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/31144 , H01L21/84 , Y10S257/90
摘要： An improved SOI structure 40 is provided. SOI structure 40 includes a semiconductor mesa 42 formed over a buried insulating layer 46 which overlies a substrate 48. Sidewall insulator regions 50 and 52 are formed along sidewalls 54 and 56, respectively, of semiconductor mesa 42. Sidewall spacers 62 and 64 are formed along sidewall insulator regions 50 and 52, respectively. Sidewall spacers 62 and 64 each include respective foot regions 66 and 68. Foot regions 66 and 68 effectively shift undercut areas 74 and 76 laterally away from semiconductor mesa 42.
摘要翻译：提供了改进的SOI结构40。 SOI结构40包括形成在覆盖衬底48的掩埋绝缘层46上的半导体台面42。侧壁绝缘体区域50和52分别沿着半导体台面42的侧壁54和56形成。侧壁间隔件62和64沿着侧壁绝缘体区域50和52。侧壁间隔件62和64各自包括相应的脚部区域66和68.脚部区域66和68有效地将底切区域74和76横向偏离半导体台面42。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式