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    • 3. 发明授权
    • Polishing method with inert gas injection
    • 惰性气体注入抛光方法
    • US08143166B2
    • 2012-03-27
    • US12046151
    • 2008-03-11
    • Feng ZhaoWu Ping LiuJohn SudijonoLaertis EconomikosLawrence A. Clevenger
    • Feng ZhaoWu Ping LiuJohn SudijonoLaertis EconomikosLawrence A. Clevenger
    • H01L21/461
    • H01L21/31053H01L21/3212
    • A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.
    • 在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。 在抛光过程中,气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。 惰性气泡密度在被抛光的基底的表面区域附近动态增加,这些表面区域易于发生凹陷和侵蚀。 增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。 抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率,使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。
    • 4. 发明申请
    • POLISHING METHOD WITH INERT GAS INJECTION
    • 具有惰性气体注入的抛光方法
    • US20090233444A1
    • 2009-09-17
    • US12046151
    • 2008-03-11
    • Feng ZhaoWu Ping LiuJohn SudijonoLaertis EconomikosLawrence A. Clevenger
    • Feng ZhaoWu Ping LiuJohn SudijonoLaertis EconomikosLawrence A. Clevenger
    • H01L21/306C09K13/00
    • H01L21/31053H01L21/3212
    • A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.
    • 在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。 在抛光过程中,气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。 惰性气泡密度在被抛光的基底的表面区域附近动态增加,这些表面区域易于发生凹陷和侵蚀。 增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。 抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率,使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。
    • 7. 发明授权
    • Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts
    • 用于DRAM阵列和栅极互连的改进的顶部氧化物层,同时提供自对准栅极触点的可扩展工艺
    • US06794242B1
    • 2004-09-21
    • US09675435
    • 2000-09-29
    • Thomas W. DyerAndreas KnorrLaertis EconomikosScott HalleRajeev MalikNorbert Arnod
    • Thomas W. DyerAndreas KnorrLaertis EconomikosScott HalleRajeev MalikNorbert Arnod
    • H01L218242
    • H01L27/10864H01L27/10891
    • A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride remaining in place. Once the devices have been formed and the gate polysilicon has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide fills the regions between and on top of the polysilicon plugs. The Top Oxide is than planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.
    • 如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管(MOSFET)的沟槽动态随机存取存储器(DRAM)阵列中,顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。 顶部氧化物通过首先形成垂直装置而形成,其中衬垫氮化物保持就位。 一旦器件已经形成并且栅极多晶硅已经被平坦化到衬底氮化物的表面之下,衬垫氮化物被剥离掉,留下栅极多晶硅插塞的顶部延伸到活性硅表面之上。 这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。 沉积的顶部氧化物填充多晶硅插塞之间和之上的区域。 顶部氧化物被平坦化回到多晶硅插塞的顶部,因此可以在通过的互连件和垂直装置的栅极之间形成接触。 顶部氧化物层用于将通过的互连与有源硅分离,从而减少两个电平之间的电容耦合,并提供用于后续互连电平的反应离子蚀刻(RIE)图案化的鲁棒蚀刻停止层。
    • 8. 发明授权
    • Method of filling isolation trenches in a substrate
    • 在衬底中填充隔离沟槽的方法
    • US06656817B2
    • 2003-12-02
    • US10136097
    • 2002-04-30
    • Ramachandra DivakaruniLaertis EconomikosByeong Y. Kim
    • Ramachandra DivakaruniLaertis EconomikosByeong Y. Kim
    • H01L2176
    • H01L21/76224H01L21/76229H01L21/763
    • Disclosed herein is a method of filling isolation trenches in a substrate. The method includes anisotropically etching trenches in a surface of a substrate and partially filling the trenches with a deposited oxide. As a consequence of the deposition, the oxide accumulates in mounds on the surface between trenches. The trenches are then filled with a supporting material of a highly flowable material such as anti-reflective coating (ARC), low-K dielectric, or a spin-on-polymer, or alternatively, a supporting material of polysilicon. A flattening process is then applied to lower the mound topography. The supporting material is then removed and the filling of the trenches with oxide is then continued. When polysilicon is used as the supporting material, the mounds are removed by wet etching prior to removing the polysilicon.
    • 本文公开了一种在衬底中填充隔离沟槽的方法。 该方法包括在衬底的表面中各向异性蚀刻沟槽,并用沉积的氧化物部分地填充沟槽。 作为沉积的结果,氧化物堆积在沟槽之间的表面上的土堆中。 然后用诸如抗反射涂层(ARC),低K电介质或旋涂聚合物的高度可流动的材料的支撑材料或者多晶硅的支撑材料填充沟槽。 然后应用扁平化过程以降低墩形地形。 然后移除支撑材料,然后继续用氧化物填充沟槽。 当使用多晶硅作为支撑材料时,在去除多晶硅之前通过湿法蚀刻去除土堆。