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1. 发明授权

US08143166B2 Polishing method with inert gas injection 有权
标题翻译：惰性气体注入抛光方法
公开(公告)号：US08143166B2
公开(公告)日：2012-03-27
申请号：US12046151
申请日：2008-03-11
申请人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
发明人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
IPC分类号： H01L21/461
CPC分类号： H01L21/31053 , H01L21/3212
摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.
摘要翻译：在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。

2. 发明申请

US20090233444A1 POLISHING METHOD WITH INERT GAS INJECTION 有权
标题翻译：具有惰性气体注入的抛光方法
公开(公告)号：US20090233444A1
公开(公告)日：2009-09-17
申请号：US12046151
申请日：2008-03-11
申请人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
发明人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
IPC分类号： H01L21/306 , C09K13/00
CPC分类号： H01L21/31053 , H01L21/3212
摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.
摘要翻译：在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。

3. 发明授权

US08177993B2 Apparatus and methods for cleaning and drying of wafers 有权
标题翻译：用于清洗和干燥晶片的装置和方法
公开(公告)号：US08177993B2
公开(公告)日：2012-05-15
申请号：US11556696
申请日：2006-11-05
申请人： Boon Meng Seah , Bei Chao Zhang , Raymond Joy , Shao Beng Law , John Sudijono , Liang Choo Hsia
发明人： Boon Meng Seah , Bei Chao Zhang , Raymond Joy , Shao Beng Law , John Sudijono , Liang Choo Hsia
IPC分类号： B44C1/22
CPC分类号： H01L21/67028 , H01L21/67051 , H01L21/6708
摘要： An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.
摘要翻译：用于蚀刻和清洁衬底的第一示例性方法和装置包括具有第一歧管和第二歧管的装置。第一歧管具有用于将化学品分配到基底上的多个喷嘴。第二歧管连接到真空源和/或干燥空气/气体源。第二示例性实施例是晶片清洁装置和方法，其使用具有毛细管喷嘴和液体毛细管喷流的歧管来清洁基底。

4. 发明申请

US20070281410A1 Spacer-less low-k dielectric processes 有权
标题翻译：无隔离低k介电过程
公开(公告)号：US20070281410A1
公开(公告)日：2007-12-06
申请号：US11447565
申请日：2006-06-05
申请人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
发明人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/8234
CPC分类号： H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
摘要翻译：第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。这用于减小寄生电容。此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。示例性实施例可以提高设备性能，例如边缘振荡器的性能。

5. 发明申请

US20070134941A1 Structure and method to prevent charge damage from e-beam curing process 有权
标题翻译：防止电子束固化过程中电荷损伤的结构和方法
公开(公告)号：US20070134941A1
公开(公告)日：2007-06-14
申请号：US11297485
申请日：2005-12-08
申请人： Huang Liu , Bei Zhang , Wuping Liu , John Sudijono , Liang Hsia
发明人： Huang Liu , Bei Zhang , Wuping Liu , John Sudijono , Liang Hsia
IPC分类号： H01L21/469
CPC分类号： H01L21/31058 , B05D3/068 , H01J2237/04735 , H01J2237/3156 , H01L21/02112 , H01L21/02274 , H01L21/02351 , H01L21/3105 , H01L21/312 , H01L21/31633 , H01L21/76825 , H01L21/76834
摘要： An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.
摘要翻译：示例性实施例是在半导体结构上固化膜的方法。我们提供由衬底和互连结构组成的半导体结构。我们提供半导体结构的电影。我们提供电子源，电子源和半导体结构之间的阳极栅极。我们通过将膜暴露于电子源通过阳极栅格的电子束来固化膜。我们通过控制阳极栅极和半导体结构之间的偏置电压来控制电子束。另一个实施例是用于固化膜的工具。

6. 发明授权

US07060613B2 Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding 有权
公开(公告)号：US07060613B2
公开(公告)日：2006-06-13
申请号：US10988692
申请日：2004-11-15
申请人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Xu Yi
发明人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Xu Yi
IPC分类号： H01L21/44
CPC分类号： H01L24/13 , H01L24/11 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/1147 , H01L2224/1308 , H01L2224/13083 , H01L2224/13147 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

7. 发明申请

US20050112799A1 Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding 失效
公开(公告)号：US20050112799A1
公开(公告)日：2005-05-26
申请号：US10988768
申请日：2004-11-15
申请人： Simon Chooi , Yakub Aliyu , Mei Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Ho , Yi Xu
发明人： Simon Chooi , Yakub Aliyu , Mei Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Ho , Yi Xu
IPC分类号： H01L21/44 , H01L21/50 , H01L21/60 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/11 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/1147 , H01L2224/1308 , H01L2224/13083 , H01L2224/13147 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

8. 发明授权

US06872633B2 Deposition and sputter etch approach to extend the gap fill capability of HDP CVD process to ≦0.10 microns 有权
标题翻译：沉积和溅射蚀刻方法将HDP CVD工艺的间隙填充能力扩展到<= 0.10微米
公开(公告)号：US06872633B2
公开(公告)日：2005-03-29
申请号：US10161014
申请日：2002-05-31
申请人： Liu Huang , John Sudijono
发明人： Liu Huang , John Sudijono
IPC分类号： H01L21/762 , H01L21/31
CPC分类号： H01L21/76229 , H01L21/76224
摘要： A method of filling an STI feature with a dielectric material using a HDP CVD technique is described. By omitting an inert carrier gas like argon in the first CVD step, a small keyhole in a SiO2 layer is formed near the top of the trench. A sputter etch step in the same CVD chamber then removes dielectric material above the keyhole. A second CVD step completely fills the STI trench which is free of voids and forms a layer above the adjacent nitride layer. The nitride layer serves as an etch stop during a CMP step to lower the level of dielectric material until it is coplanar with the nitride layer. The method is low cost since all deposition and sputter etch steps are performed in an existing CVD tool and the same tool is useful in forming trenches of various sizes ranging from below 0.13 micron to above 0.25 micron.
摘要翻译：描述了使用HDP CVD技术用电介质材料填充STI特征的方法。通过在第一CVD步骤中省略诸如氩的惰性载气，在沟槽的顶部附近形成SiO 2层中的小键孔。然后在相同的CVD室中的溅射蚀刻步骤除去键孔上方的介电材料。第二CVD步骤完全填充没有空隙的STI沟槽，并在相邻的氮化物层上方形成一层。在CMP步骤期间，氮化物层用作蚀刻停止层，以降低电介质材料的水平，直到其与氮化物层共面。该方法是低成本的，因为在现有的CVD工具中进行所有沉积和溅射蚀刻步骤，并且相同的工具可用于形成从0.13微米至0.25微米以下的各种尺寸的沟槽。

9. 发明授权

US06821888B2 Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding 失效
标题翻译：使用导电聚合物铜/铜表面键合方法应用于IC芯片接合
公开(公告)号：US06821888B2
公开(公告)日：2004-11-23
申请号：US10076244
申请日：2002-02-13
申请人： Yakub Aliyu , Simon Chooi , Meisheng Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy
发明人： Yakub Aliyu , Simon Chooi , Meisheng Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy
IPC分类号： H01L2144
CPC分类号： H01L24/13 , H01L24/11 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/1147 , H01L2224/1308 , H01L2224/13083 , H01L2224/13147 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
摘要翻译：提供了具有暴露的金属端接垫的半导体芯片，以及在其上具有对应的暴露的金属凸块的单独的基板。在暴露的金属端接垫上形成导电聚合物塞。在导电聚合物塞上形成一个符合标准的界面层。半导体芯片的导电聚合物插塞与相应的金属凸块对准。导电聚合物塞上的一致界面层与相应的金属凸块配合。一致的界面层被热分解，粘附和永久地附着导电聚合物塞与相应的金属凸块。还公开了形成和图案化羰基镍层的方法。

10. 发明授权

US06706625B1 Copper recess formation using chemical process for fabricating barrier cap for lines and vias 有权
标题翻译：用于制造线路和通孔的屏障盖的化学工艺的铜凹槽形成
公开(公告)号：US06706625B1
公开(公告)日：2004-03-16
申请号：US10313499
申请日：2002-12-06
申请人： John Sudijono , Liang Ch O Hsia , Liu Wu Ping
发明人： John Sudijono , Liang Ch O Hsia , Liu Wu Ping
IPC分类号： H01L214763
CPC分类号： H01L21/76849
摘要： A method of fabricating a planarized barrier cap layer over a metal structure comprising the following steps. A substrate having an opening formed therein is provided. The substrate having an upper surface. A planarized metal structure is formed within the opening. The planarized metal structure being substantially planar with the upper surface of the substrate. A portion of the planarized metal structure is removed using a reverse-electrochemical plating process to recess the metal structure from the upper surface of the substrate. A barrier cap layer is formed over the substrate and the recessed metal structure. The excess of the barrier cap layer is removed from over the substrate by a planarization process to form the planarized barrier cap layer over the metal structure.
摘要翻译：一种在金属结构上制造平坦化的阻挡盖层的方法，包括以下步骤。提供其中形成有开口的基板。基板具有上表面。平面化的金属结构形成在开口内。平坦化的金属结构与衬底的上表面基本上是平面的。使用反电化学电镀工艺去除平坦化的金属结构的一部分，以从衬底的上表面凹入金属结构。在衬底和凹陷金属结构之上形成阻挡层。通过平坦化处理从衬底上去除过量的阻挡层，以在金属结构上形成平坦化的阻挡层。

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