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1. 发明授权

US06656817B2 Method of filling isolation trenches in a substrate 失效
标题翻译：在衬底中填充隔离沟槽的方法
公开(公告)号：US06656817B2
公开(公告)日：2003-12-02
申请号：US10136097
申请日：2002-04-30
申请人： Ramachandra Divakaruni , Laertis Economikos , Byeong Y. Kim
发明人： Ramachandra Divakaruni , Laertis Economikos , Byeong Y. Kim
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/76229 , H01L21/763
摘要： Disclosed herein is a method of filling isolation trenches in a substrate. The method includes anisotropically etching trenches in a surface of a substrate and partially filling the trenches with a deposited oxide. As a consequence of the deposition, the oxide accumulates in mounds on the surface between trenches. The trenches are then filled with a supporting material of a highly flowable material such as anti-reflective coating (ARC), low-K dielectric, or a spin-on-polymer, or alternatively, a supporting material of polysilicon. A flattening process is then applied to lower the mound topography. The supporting material is then removed and the filling of the trenches with oxide is then continued. When polysilicon is used as the supporting material, the mounds are removed by wet etching prior to removing the polysilicon.
摘要翻译：本文公开了一种在衬底中填充隔离沟槽的方法。该方法包括在衬底的表面中各向异性蚀刻沟槽，并用沉积的氧化物部分地填充沟槽。作为沉积的结果，氧化物堆积在沟槽之间的表面上的土堆中。然后用诸如抗反射涂层（ARC），低K电介质或旋涂聚合物的高度可流动的材料的支撑材料或者多晶硅的支撑材料填充沟槽。然后应用扁平化过程以降低墩形地形。然后移除支撑材料，然后继续用氧化物填充沟槽。当使用多晶硅作为支撑材料时，在去除多晶硅之前通过湿法蚀刻去除土堆。

2. 发明授权

US07737502B2 Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain 有权
标题翻译：用于提高源/漏极的应变Si / SGOI结构上的多栅极氧化和侧壁保护的提高的STI工艺
公开(公告)号：US07737502B2
公开(公告)日：2010-06-15
申请号：US11351801
申请日：2006-02-10
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
IPC分类号： H01L27/088
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

3. 发明申请

US20090001466A1 METHOD OF FORMING AN SOI SUBSTRATE CONTACT 有权
标题翻译：形成SOI衬底接触的方法
公开(公告)号：US20090001466A1
公开(公告)日：2009-01-01
申请号：US11769914
申请日：2007-06-28
申请人： Haining S. Yang , Ramachandra Divakaruni , Byeong Y. Kim , Junedong Lee , Gaku Sudo
发明人： Haining S. Yang , Ramachandra Divakaruni , Byeong Y. Kim , Junedong Lee , Gaku Sudo
IPC分类号： H01L21/4763 , H01L27/01
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76254 , H01L21/823807 , H01L21/823871 , H01L21/84 , H01L29/7843
摘要： A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region shares an edge with the SOI layer. A dielectric layer then is deposited atop the conformal layer and the trench isolation region, after which a second opening is formed which is aligned with the first opening, the second opening extending through the dielectric layer to expose the bulk semiconductor region. Finally, the conductive via is formed in the second opening.
摘要翻译：提供了形成用于接触绝缘体上半导体（“SOI”）衬底的体半导体区域的导电通孔的方法。第一开口形成在覆盖沟槽隔离区域的共形层中，其中沟槽隔离区域与SOI层共享边缘。然后在保形层和沟槽隔离区的顶部沉积电介质层，然后形成与第一开口对准的第二开口，第二开口延伸穿过电介质层以暴露体半导体区域。最后，在第二开口中形成导电通孔。

4. 发明授权

US07867893B2 Method of forming an SOI substrate contact 有权
标题翻译：形成SOI衬底接触的方法
公开(公告)号：US07867893B2
公开(公告)日：2011-01-11
申请号：US11769914
申请日：2007-06-28
申请人： Haining S. Yang , Ramachandra Divakaruni , Byeong Y. Kim , Junedong Lee , Gaku Sudo
发明人： Haining S. Yang , Ramachandra Divakaruni , Byeong Y. Kim , Junedong Lee , Gaku Sudo
IPC分类号： H01L27/01
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76254 , H01L21/823807 , H01L21/823871 , H01L21/84 , H01L29/7843
摘要： A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region shares an edge with the SOI layer. A dielectric layer then is deposited atop the conformal layer and the trench isolation region, after which a second opening is formed which is aligned with the first opening, the second opening extending through the dielectric layer to expose the bulk semiconductor region. Finally, the conductive via is formed in the second opening.
摘要翻译：提供了形成用于接触绝缘体上半导体（“SOI”）衬底的体半导体区域的导电通孔的方法。第一开口形成在覆盖沟槽隔离区域的共形层中，其中沟槽隔离区域与SOI层共享边缘。然后在保形层和沟槽隔离区的顶部沉积电介质层，然后形成与第一开口对准的第二开口，第二开口延伸穿过电介质层以暴露体半导体区域。最后，在第二开口中形成导电通孔。

5. 发明授权

US07037794B2 Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain 失效
标题翻译：提高了用于多栅极氧化和侧壁保护的STI工艺，在应变Si / SGOI结构上具有升高的源极/漏极
公开(公告)号：US07037794B2
公开(公告)日：2006-05-02
申请号：US10709963
申请日：2004-06-09
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

6. 发明授权

US08679938B2 Shallow trench isolation for device including deep trench capacitors 失效
标题翻译：用于包括深沟槽电容器的器件的浅沟槽隔离
公开(公告)号：US08679938B2
公开(公告)日：2014-03-25
申请号：US13366576
申请日：2012-02-06
申请人： Sunfei Fang , Oleg Gluschenkov , Byeong Y. Kim , Rishikesh Krishnan , Daewon Yang
发明人： Sunfei Fang , Oleg Gluschenkov , Byeong Y. Kim , Rishikesh Krishnan , Daewon Yang
IPC分类号： H01L21/20
CPC分类号： H01L27/10861 , H01L21/76224 , H01L29/66181 , H01L29/945
摘要： A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.
摘要翻译：在包括沟槽电容元件的器件的有源区中形成浅沟槽隔离（STI）的方法，包括金属板和高k电介质的沟槽电容元件包括在器件的有源区中蚀刻STI沟槽，其中所述STI沟槽直接邻近所述沟槽电容元件的金属板或高k电介质中的至少一个; 以及在所述STI沟槽中形成氧化物衬垫，其中所述氧化物衬垫选择性地形成到所述金属板或高k电介质，其中形成所述氧化物衬垫在约600℃或更低的温度下进行。

7. 发明授权

US08629017B2 Structure and method to form EDRAM on SOI substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US08629017B2
公开(公告)日：2014-01-14
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

8. 发明授权

US08227311B2 Method of forming enhanced capacitance trench capacitor 有权
标题翻译：形成增强型电容沟槽电容器的方法
公开(公告)号：US08227311B2
公开(公告)日：2012-07-24
申请号：US12900095
申请日：2010-10-07
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L21/8242
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：提供一种制造沟槽电容器的方法，其中衬底的半导体区域的材料组成在其中的至少一个分量的量中变化，使得该量在至少两个不同值之间多次与深度交替。例如，半导体合金中的掺杂剂的浓度或第二半导体材料的重量百分比可以在较高和较低值之间的深度之间交替多次。在这种方法中，可以以取决于材料组成的方式蚀刻半导体区域，以形成具有在与半导体区域的主表面的深度方向上起伏的内表面的沟槽。这种方法还可以包括形成具有波状电容器介电层的沟槽电容器，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

9. 发明授权

US08188528B2 Structure and method to form EDRAM on SOI substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US08188528B2
公开(公告)日：2012-05-29
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

10. 发明申请

US20120086064A1 METHOD OF FORMING ENHANCED CAPACITANCE TRENCH CAPACITOR 有权
标题翻译：形成增强型电容式电容器的方法
公开(公告)号：US20120086064A1
公开(公告)日：2012-04-12
申请号：US12900095
申请日：2010-10-07
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：提供一种制造沟槽电容器的方法，其中衬底的半导体区域的材料组成在其中的至少一个分量的量中变化，使得该量在至少两个不同值之间多次与深度交替。例如，半导体合金中的掺杂剂的浓度或第二半导体材料的重量百分比可以在较高和较低值之间的深度之间交替多次。在这种方法中，可以以取决于材料组成的方式蚀刻半导体区域，以形成具有在与半导体区域的主表面的深度方向上起伏的内表面的沟槽。这种方法还可以包括形成具有波状电容器介电层的沟槽电容器，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

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