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1. 发明授权

US08143166B2 Polishing method with inert gas injection 有权
标题翻译：惰性气体注入抛光方法
公开(公告)号：US08143166B2
公开(公告)日：2012-03-27
申请号：US12046151
申请日：2008-03-11
申请人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
发明人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
IPC分类号： H01L21/461
CPC分类号： H01L21/31053 , H01L21/3212
摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.
摘要翻译：在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。

2. 发明申请

US20090233444A1 POLISHING METHOD WITH INERT GAS INJECTION 有权
标题翻译：具有惰性气体注入的抛光方法
公开(公告)号：US20090233444A1
公开(公告)日：2009-09-17
申请号：US12046151
申请日：2008-03-11
申请人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
发明人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
IPC分类号： H01L21/306 , C09K13/00
CPC分类号： H01L21/31053 , H01L21/3212
摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.
摘要翻译：在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。

3. 发明申请

US20120194792A1 METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY 有权
标题翻译：使用模拟或测量的地形来预测地震聚焦误差的方法和系统
公开(公告)号：US20120194792A1
公开(公告)日：2012-08-02
申请号：US13014803
申请日：2011-01-27
申请人： Brian Christopher Sapp , Choongyeun Cho , Lawrence A. Clevenger , Laertis Economikos , Bernhard R. Liegl , Kevin S. Petrarca , Roger Allan Quon
发明人： Brian Christopher Sapp , Choongyeun Cho , Lawrence A. Clevenger , Laertis Economikos , Bernhard R. Liegl , Kevin S. Petrarca , Roger Allan Quon
IPC分类号： G03B27/52
CPC分类号： G03F7/7065 , G03F7/70066 , G03F7/705 , G03F7/70525 , G03F7/70641 , G03F9/7026 , G06F17/5009 , G06F17/5081
摘要： A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.
摘要翻译：公开了使用芯片形貌数据来预测光刻聚焦误差的方法和系统。可以测量或模拟地形数据的芯片地形数据。平面最适合地形数据，并计算残差。然后，残差用于对聚焦误差进行预测。金属与电介质的密度比也可用作确定预测的聚焦误差的因素。

4. 发明授权

US08792080B2 Method and system to predict lithography focus error using simulated or measured topography 有权
标题翻译：使用模拟或测量地形预测光刻焦点误差的方法和系统
公开(公告)号：US08792080B2
公开(公告)日：2014-07-29
申请号：US13014803
申请日：2011-01-27
申请人： Brian Christopher Sapp , Choongyeun Cho , Lawrence A. Clevenger , Laertis Economikos , Bernhard R. Liegl , Kevin S. Petrarca , Roger Allan Quon
发明人： Brian Christopher Sapp , Choongyeun Cho , Lawrence A. Clevenger , Laertis Economikos , Bernhard R. Liegl , Kevin S. Petrarca , Roger Allan Quon
IPC分类号： G03B27/52 , G03F7/20 , G03F9/00
CPC分类号： G03F7/7065 , G03F7/70066 , G03F7/705 , G03F7/70525 , G03F7/70641 , G03F9/7026 , G06F17/5009 , G06F17/5081
摘要： A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.
摘要翻译：公开了使用芯片形貌数据来预测光刻聚焦误差的方法和系统。可以测量或模拟地形数据的芯片地形数据。平面最适合地形数据，并计算残差。然后，残差用于对聚焦误差进行预测。金属与电介质的密度比也可用作确定预测的聚焦误差的因素。

5. 发明授权

US09281278B2 Interconnects with improved TDDB 有权
标题翻译：与改进的TDDB互连
公开(公告)号：US09281278B2
公开(公告)日：2016-03-08
申请号：US13286224
申请日：2011-11-01
申请人： Jing Hui Li , Wu Ping Liu , Lawrence A. Clevenger
发明人： Jing Hui Li , Wu Ping Liu , Lawrence A. Clevenger
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.
摘要翻译：提出了一种形成半导体器件的方法。提供了在其上形成有介电层的基板。在介电层上形成第一上蚀刻停止层。第一上蚀刻停止层包括第一电介质材料。将电介质层和第一上蚀刻停止层图案化以形成互连开口。互连开口填充有导电材料以形成互连。互连和第一上蚀刻停止层具有共面的顶表面。第二上蚀刻停止层形成在共面顶表面上。第二上蚀刻停止层包括与第一材料具有足够粘合力以减少导电材料扩散的第二材料。

6. 发明授权

US08053361B2 Interconnects with improved TDDB 有权
标题翻译：与改进的TDDB互连
公开(公告)号：US08053361B2
公开(公告)日：2011-11-08
申请号：US12203924
申请日：2008-09-04
申请人： Jing Hui Li , Wu Ping Liu , Lawrence A. Clevenger
发明人： Jing Hui Li , Wu Ping Liu , Lawrence A. Clevenger
IPC分类号： H01L23/52
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.
摘要翻译：提出了一种形成半导体器件的方法。提供了在其上形成有介电层的基板。在介电层上形成第一上蚀刻停止层。第一上蚀刻停止层包括第一电介质材料。将电介质层和第一上蚀刻停止层图案化以形成互连开口。互连开口填充有导电材料以形成互连。互连和第一上蚀刻停止层具有共面的顶表面。第二上蚀刻停止层形成在共面顶表面上。第二上蚀刻停止层包括与第一材料具有足够粘合力以减少导电材料扩散的第二材料。

7. 发明授权

US09634165B2 Regeneration method for restoring photovoltaic cell efficiency 有权
公开(公告)号：US09634165B2
公开(公告)日：2017-04-25
申请号：US12887121
申请日：2010-09-21
申请人： Lawrence A. Clevenger , Rainer Krause , Zhengwen Li , Gerd Pfeiffer , Kevin Prettyman , Brian C. Sapp
发明人： Lawrence A. Clevenger , Rainer Krause , Zhengwen Li , Gerd Pfeiffer , Kevin Prettyman , Brian C. Sapp
IPC分类号： H01L31/00 , H01L31/042 , H01L31/18 , H01L31/0376
CPC分类号： H02S40/40 , H01L31/03767 , H01L31/042 , H01L31/1864 , H02S50/10 , Y02E10/50 , Y02P70/521 , Y10T29/413
摘要： An apparatus, system, and method are disclosed for restoring efficiency of a photovoltaic cell. An illumination module illuminates photovoltaic cells so the cells receive a time integrated irradiance equivalent to at least 5 hours of solar illumination. After illumination, an annealing module anneals the photovoltaic cells at a temperature above 90 degrees Celsius for a minimum of 10 minutes. In one embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 20 hours of solar illumination. In another embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 16 hours of solar illumination while being heated to at least 50 degrees Celsius. In another embodiment, a solar concentrator irradiates the photovoltaic cells in sunlight for at least 10 hours and increases the irradiance of solar illumination on the cells by a factor of 2 to 5.

8. 发明授权

US08809183B2 Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer 有权
标题翻译：互连结构与选择性导电盖和电介质盖层之间的平面界面
公开(公告)号：US08809183B2
公开(公告)日：2014-08-19
申请号：US12887010
申请日：2010-09-21
申请人： Griselda Bonilla , Lawrence A. Clevenger , Elbert E. Huang , Satyanarayana V. Nitta , Shom Ponoth
发明人： Griselda Bonilla , Lawrence A. Clevenger , Elbert E. Huang , Satyanarayana V. Nitta , Shom Ponoth
IPC分类号： H01L21/4763
CPC分类号： H01L23/5329 , H01L21/28562 , H01L21/288 , H01L21/76825 , H01L21/76826 , H01L21/76834 , H01L21/76835 , H01L21/76849 , H01L21/76861 , H01L21/76862 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.
摘要翻译：选择性导电盖通过对金属互连结构的暴露的下面的电介质表面可选择的化学镀层沉积在金属线的暴露的金属表面上。介电材料层沉积在选择性导电盖和暴露的下面的介质层上，而不需要预清洗。介电材料层被平坦化以形成与选择性导电帽的最顶面共面的水平平面。执行预清洁，并且在选择性导电盖和介电材料层的平坦化表面上沉积电介质盖层。由于包括由预清洗层损坏的表面的界面垂直偏离金属线的最上表面，所以金属线中的金属沿着界面的电迁移减少或消除。

9. 发明授权

US08772941B2 Circuit structure with low dielectric constant regions 有权
标题翻译：具有低介电常数区域的电路结构
公开(公告)号：US08772941B2
公开(公告)日：2014-07-08
申请号：US12206314
申请日：2008-09-08
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
IPC分类号： H01L23/522
CPC分类号： H01L21/76808 , H01L21/7682
摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
摘要翻译：一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

10. 发明授权

US08614115B2 Photovoltaic solar cell device manufacture 失效
标题翻译：光伏太阳能电池器件制造
公开(公告)号：US08614115B2
公开(公告)日：2013-12-24
申请号：US12916236
申请日：2010-10-29
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
IPC分类号： H01L21/00 , H01L31/18
CPC分类号： H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.
摘要翻译：光伏太阳能电池器件的制造方法包括以下。形成具有第一掺杂密度的p-n结。通过引入第二掺杂密度以形成用于双发射器应用的高掺杂区域来增强p-n结的形成。高掺杂区域由与p-n结的形成集成的掩模工艺限定，产生高掺杂区域的掩模图案。根据高掺杂区域的掩模图案发生高掺杂区域的金属化。

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