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1. 发明申请

US20130201744A1 DMA ARCHITECTURE FOR NAND-TYPE FLASH MEMORY 失效
标题翻译： NAND型闪存存储器的DMA架构
公开(公告)号：US20130201744A1
公开(公告)日：2013-08-08
申请号：US13364971
申请日：2012-02-02
申请人： Mauro Pagliato , Giulio Martinozzi , Francesco Pessina
发明人： Mauro Pagliato , Giulio Martinozzi , Francesco Pessina
IPC分类号： G11C7/10 , G11C11/413 , G11C5/06
CPC分类号： G11C7/1039 , G11C16/00 , G11C16/0483 , G11C29/1201 , G11C29/50004 , G11C2029/5006
摘要： A device includes a nonvolatile memory array, a Static Random Access Memory (SRAM) array including a plurality of bit lines, including first and second bit lines paired with each other, and a pad. A first circuit is coupled between the nonvolatile memory array and the first and second bit lines, and interfaces with the SRAM array. A second circuit is coupled between the pad and the first and second bit lines, and interfaces with the SRAM array. A control circuit performs a first operation to access the nonvolatile memory array via the SRAM array and the first and second circuits and performs a second operation by producing an electrical path connecting from the pad to the nonvolatile memory array through at least one of the first and second bit lines of the SRAM array without intervening at least one of the first and second circuits.
摘要翻译：一种设备包括非易失性存储器阵列，包括多个位线的静态随机存取存储器（SRAM）阵列，其包括彼此配对的第一和第二位线以及焊盘。第一电路耦合在非易失性存储器阵列与第一和第二位线之间，并与SRAM阵列接口。第二电路耦合在焊盘和第一和第二位线之间，并与SRAM阵列的接口连接。控制电路执行第一操作以经由SRAM阵列和第一和第二电路访问非易失性存储器阵列，并且通过产生通过第一和第二电路中的至少一个产生从焊盘连接到非易失性存储器阵列的电路来执行第二操作 SRAM阵列的第二位线，而不插入第一和第二电路中的至少一个。

2. 发明申请

US20120224439A1 MASK-WRITE APPARATUS FOR A SRAM CELL 失效
标题翻译：用于SRAM单元的MASK-WRITE设备
公开(公告)号：US20120224439A1
公开(公告)日：2012-09-06
申请号：US13040766
申请日：2011-03-04
申请人： Giulio Martinozzi , Mauro Pagliato
发明人： Giulio Martinozzi , Mauro Pagliato
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/1009 , G11C11/419
摘要： Disclosed herein is a device that comprises a SRAM cell, a pair of bit-lines coupled with the SRAM cell, a writing circuit producing at first and second output nodes thereof true and complementary data signals responsive to data to be written, a first pass transistor coupled between one of the pair of the bit-lines and the first output node of the writing circuit, a second pass transistor coupled between the other of the pair of bit lines and the second output node of the writing circuit; and a mask-write circuit configured to render both of the first and second pass transistors conductive in a write operation and render selected one or ones of first and second pass transistors non-conductive in a write-mask operation.
摘要翻译：本文公开了一种包括SRAM单元，与SRAM单元耦合的一对位线的装置，响应于待写入数据的第一和第二输出节点产生真实和互补数据信号的写入电路，第一传输晶体管耦合在所述一对位线之一和所述写入电路的所述第一输出节点之间;耦合在所述一对位线中的另一个和所述写入电路的所述第二输出节点之间的第二传输晶体管; 以及掩模写入电路，被配置为在写入操作中使第一和第二通过晶体管都导通，并且在写入掩模操作中使第一和第二通过晶体管中的一个或多个不导通。

3. 发明授权

US08724361B2 DMA architecture for NAND-type flash memory 失效
标题翻译： NAND型闪存的DMA架构
公开(公告)号：US08724361B2
公开(公告)日：2014-05-13
申请号：US13364971
申请日：2012-02-02
申请人： Mauro Pagliato , Giulio Martinozzi , Francesco Pessina
发明人： Mauro Pagliato , Giulio Martinozzi , Francesco Pessina
IPC分类号： G11C5/06
CPC分类号： G11C7/1039 , G11C16/00 , G11C16/0483 , G11C29/1201 , G11C29/50004 , G11C2029/5006
摘要： A device includes a nonvolatile memory array, a Static Random Access Memory (SRAM) array including a plurality of bit lines, including first and second bit lines paired with each other, and a pad. A first circuit is coupled between the nonvolatile memory array and the first and second bit lines, and interfaces with the SRAM array. A second circuit is coupled between the pad and the first and second bit lines, and interfaces with the SRAM array. A control circuit performs a first operation to access the nonvolatile memory array via the SRAM array and the first and second circuits and performs a second operation by producing an electrical path connecting from the pad to the nonvolatile memory array through at least one of the first and second bit lines of the SRAM array without intervening at least one of the first and second circuits.
摘要翻译：一种设备包括非易失性存储器阵列，包括多个位线的静态随机存取存储器（SRAM）阵列，其包括彼此配对的第一和第二位线以及焊盘。第一电路耦合在非易失性存储器阵列与第一和第二位线之间，并与SRAM阵列接口。第二电路耦合在焊盘和第一和第二位线之间，并与SRAM阵列的接口连接。控制电路执行第一操作以经由SRAM阵列和第一和第二电路访问非易失性存储器阵列，并且通过产生通过第一和第二电路中的至少一个产生从焊盘连接到非易失性存储器阵列的电路来执行第二操作 SRAM阵列的第二位线，而不插入第一和第二电路中的至少一个。

4. 发明授权

US08391086B2 Mask-write apparatus for a SRAM cell 失效
标题翻译：用于SRAM单元的掩模写装置
公开(公告)号：US08391086B2
公开(公告)日：2013-03-05
申请号：US13040766
申请日：2011-03-04
申请人： Giulio Martinozzi , Mauro Pagliato
发明人： Giulio Martinozzi , Mauro Pagliato
IPC分类号： G11C7/00
CPC分类号： G11C7/1009 , G11C11/419
摘要： Disclosed herein is a device that comprises a SRAM cell, a pair of bit-lines coupled with the SRAM cell, a writing circuit producing at first and second output nodes thereof true and complementary data signals responsive to data to be written, a first pass transistor coupled between one of the pair of the bit-lines and the first output node of the writing circuit, a second pass transistor coupled between the other of the pair of bit lines and the second output node of the writing circuit; and a mask-write circuit configured to render both of the first and second pass transistors conductive in a write operation and render selected one or ones of first and second pass transistors non-conductive in a write-mask operation.
摘要翻译：本文公开了一种包括SRAM单元，与SRAM单元耦合的一对位线的装置，响应于待写入数据的第一和第二输出节点产生真实和互补数据信号的写入电路，第一传输晶体管耦合在所述一对位线之一和所述写入电路的所述第一输出节点之间;耦合在所述一对位线中的另一个和所述写入电路的所述第二输出节点之间的第二传输晶体管; 以及掩模写入电路，被配置为在写入操作中使第一和第二通过晶体管都导通，并且在写入掩模操作中使第一和第二通过晶体管中的一个或多个不导通。

5. 发明授权

US07136305B2 Sense amplifier with equalizer 有权
标题翻译：带均衡器的感应放大器
公开(公告)号：US07136305B2
公开(公告)日：2006-11-14
申请号：US10913788
申请日：2004-08-06
申请人： Mauro Pagliato , Massimo Montanaro , Paolo Rolandi
发明人： Mauro Pagliato , Massimo Montanaro , Paolo Rolandi
IPC分类号： G11C16/06 , G11C7/02
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062 , G11C7/067 , G11C16/28
摘要： A sense amplifier is provided that includes a measure branch receiving an input current to be detected, a reference branch receiving a reference current, and an equalizing circuit including a comparator. The equalizing circuit selectively equalizes a measure node of the measure branch with a reference node of the reference branch, and the comparator compares a voltage at the measure node of the measure branch with a voltage at the reference node of the reference branch. The equalizing circuit is such that, when activated, equalization of the measure node with the reference node is virtual and substantially does not involve a flow of current between the measure node and the reference node of the reference branch. The sense amplifier is particularly suited for reading memory cells of a semiconductor memory. Also provided is a method for sensing an input current.
摘要翻译：提供了一种读出放大器，其包括接收待检测的输入电流的测量分支，接收参考电流的参考分支和包括比较器的均衡电路。均衡电路选择性地将测量分支的测量节点与参考分支的参考节点相等，并且比较器将测量分支的测量节点处的电压与参考分支的参考节点处的电压进行比较。均衡电路使得当被激活时，具有参考节点的测量节点的均衡是虚拟的并且基本上不涉及测量节点和参考分支的参考节点之间的电流。读出放大器特别适用于读取半导体存储器的存储单元。还提供了用于感测输入电流的方法。

6. 发明申请

US20050063236A1 Sense amplifier 有权
标题翻译：感应放大器
公开(公告)号：US20050063236A1
公开(公告)日：2005-03-24
申请号：US10913788
申请日：2004-08-06
申请人： Mauro Pagliato , Massimo Montanaro , Paolo Rolandi
发明人： Mauro Pagliato , Massimo Montanaro , Paolo Rolandi
IPC分类号： G11C7/06 , G11C11/56 , G11C16/28 , G11C11/34
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062 , G11C7/067 , G11C16/28
摘要： A sense amplifier is provided that includes a measure branch receiving an input current to be detected, a reference branch receiving a reference current, equalizing means, and a comparator. The equalizing means selectively equalizes a measure node of the measure branch with a reference node of the reference branch, and the comparator compares a voltage at the measure node of the measure branch with a voltage at the reference node of the reference branch. The equalizing means are such that, when activated, equalization of the measure node with the reference node is virtual and substantially does not involve a flow of current between the measure node and the reference node of the reference branch. The sense amplifier is particularly suited for reading memory cells of a semiconductor memory. Also provided is a method for sensing an input current.
摘要翻译：提供了一种读出放大器，其包括接收待检测的输入电流的测量分支，接收参考电流的参考分支，均衡装置和比较器。均衡装置选择性地将测量分支的测量节点与参考分支的参考节点进行均衡，并且比较器将测量分支的测量节点处的电压与参考分支的参考节点处的电压进行比较。均衡装置使得当激活时，具有参考节点的测量节点的均衡是虚拟的并且基本上不涉及测量节点和参考分支的参考节点之间的电流。读出放大器特别适用于读取半导体存储器的存储单元。还提供了用于感测输入电流的方法。

7. 发明授权

US06657895B2 Reading circuit and method for a multilevel non-volatile memory 有权
公开(公告)号：US06657895B2
公开(公告)日：2003-12-02
申请号：US10118660
申请日：2002-04-08
申请人： Mauro Pagliato , Paolo Rolandi , Massimo Montanaro
发明人： Mauro Pagliato , Paolo Rolandi , Massimo Montanaro
IPC分类号： G11C1600
CPC分类号： G11C11/5642 , G11C11/56 , G11C11/5621 , G11C2211/5632
摘要： Described herein is an asynchronous serial dichotomic sense amplifier comprising a first comparator stage having a first input receiving the cell current flowing in the multilevel memory cell, the content of which is to be read, a second input receiving a first reference current, and an output supplying the first of the bits stored in the multilevel memory cell; a multiplexer stage having a selection input connected to the output of the first comparator stage, a first signal input receiving a second reference current, a second signal input receiving a third reference current, and a signal output selectively connectable to the first or the second signal input depending on the logic level present on the selection input; and a second comparator stage having a first input receiving the cell current, a second input connected to the signal output of the multiplexer stage, and an output supplying the second of the bits stored in the multilevel memory cell.

8. 发明授权

US06605985B2 High-efficiency power charge pump supplying high DC output currents 有权
标题翻译：提供高直流输出电流的高效率电荷泵
公开(公告)号：US06605985B2
公开(公告)日：2003-08-12
申请号：US10162135
申请日：2002-06-03
申请人： Mauro Pagliato , Paolo Rolandi , Giorgio Oddone , Marco Fontana
发明人： Mauro Pagliato , Paolo Rolandi , Giorgio Oddone , Marco Fontana
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/077
摘要： The voltage applied to the gate terminals of the charging transistors and charge-transfer transistors of two parallel pumping branches forming a charge pump is a boosted voltage generated internally and supplied in a crosswise manner. In particular, for driving the charge pump, first and second driving signals are generated respectively for the first and for the second pumping branch via a first and respectively a second driving circuit; the first and second driving signals are also supplied respectively to a first and to a second auxiliary charge pump to obtain respectively first and second voltage-boosted signals; and the first and second boosted voltages are respectively supplied to the second and to the first driving circuit.
摘要翻译：施加到形成电荷泵的两个并联泵浦支路的充电晶体管和电荷转移晶体管的栅极端子的电压是内部产生的升压电压并以交叉方式提供。特别地，为了驱动电荷泵，分别通过第一和第二驱动电路为第一和第二泵分支产生第一和第二驱动信号; 第一和第二驱动信号也分别提供给第一和第二辅助电荷泵，以分别获得第一和第二电压升高信号; 并且第一和第二升压电压分别提供给第二和第二驱动电路。

9. 发明授权

US08599615B2 Memory device in particular extra array configured therein for configuration and redundancy information 失效
标题翻译：存储器件特别地配置在其中用于配置和冗余信息的额外阵列
公开(公告)号：US08599615B2
公开(公告)日：2013-12-03
申请号：US13275708
申请日：2011-10-18
申请人： Simone Bartoli , Mauro Pagliato , Diego Della Mina
发明人： Simone Bartoli , Mauro Pagliato , Diego Della Mina
IPC分类号： G11C11/04 , G11C16/06
CPC分类号： G11C29/789
摘要： Disclosed herein is a device that includes a plurality of first word lines each extending from an associated one of the first terminals in a second direction toward to the second terminals and terminating between the first and second terminals, the second direction being substantially perpendicular to the first direction, and a plurality of second word lines each extending from an associated one of the second terminals in a third direction toward to the first terminals and terminating near to an end of an associated one of the first word lines, the third direction being opposite to the second direction, each of the second word lines being substantially aligned with an associated one of the first word lines.
摘要翻译：本文公开了一种装置，其包括多个第一字线，每个第一字线从第一端子中的相关联的一个在第二方向朝向第二端子延伸并且终止于第一和第二端子之间，第二方向基本上垂直于第一方向和多个第二字线，每个第二字线在第三方向上从相关联的一个第二端子延伸到第一端子并且终止于相关联的第一字线之一的端部，第三方向与第一方向相反所述第二方向，所述第二字线中的每一条基本上与所述第一字线中的相关联的一条对齐。

10. 发明申请

US20080037301A1 HIGH VOLTAGE GENERATOR OF THE DAC-CONTROLLED TYPE 有权
标题翻译： DAC控制型高压发电机
公开(公告)号：US20080037301A1
公开(公告)日：2008-02-14
申请号：US11463260
申请日：2006-08-08
申请人： Marco Fontana , Mauro Pagliato , Chiara De Berti , Marco Spinelli , Davide Bitonti
发明人： Marco Fontana , Mauro Pagliato , Chiara De Berti , Marco Spinelli , Davide Bitonti
IPC分类号： H02M3/18
CPC分类号： H02M3/073 , G11C5/145 , G11C5/147 , H02M1/36 , H02M2001/0025
摘要： A high voltage generator of the DAC-controlled type, has an input terminal connected to a first voltage reference and an output terminal providing an output voltage and comprises at least a voltage control circuit and a charge pump circuit inserted, in series to each other, between the input and output terminals of the high voltage generator, and an output regulator connected to the output terminal of the high voltage generator and comprising at least a digital-to-analog converter or DAC. The output regulator further comprises at least an additional current regulation portion connected to the output terminal of the high voltage generator through a first resistive element of the output regulator as well to an enabling terminal which provides an enabling signal, the additional current regulation portion being supplied by a second voltage reference having a voltage level higher than a voltage level of the first voltage reference.
摘要翻译： DAC控制型的高电压发生器具有连接到第一电压基准的输入端和提供输出电压的输出端，并且至少包括彼此串联插入的电压控制电路和电荷泵电路，在高压发生器的输入和输出端之间以及连接到高电压发生器的输出端的输出调节器，至少包括一个数模转换器或DAC。输出调节器还包括至少一个额外的电流调节部分，其通过输出调节器的第一电阻元件连接到高电压发生器的输出端子，以及提供使能信号的使能端子，附加电流调节部分被提供通过具有高于第一参考电压的电压电平的电压电平的第二参考电压。

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