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1. 发明申请

US20090006810A1 MECHANISM TO SUPPORT GENERIC COLLECTIVE COMMUNICATION ACROSS A VARIETY OF PROGRAMMING MODELS 失效
标题翻译：通过各种编程模式支持通用集体交流的机制
公开(公告)号：US20090006810A1
公开(公告)日：2009-01-01
申请号：US11768669
申请日：2007-06-26
申请人： Gheorghe Almasi , Gabor Dozsa , Sameer Kumar
发明人： Gheorghe Almasi , Gabor Dozsa , Sameer Kumar
IPC分类号： G06F15/00
CPC分类号： G06F9/54
摘要： A system and method for supporting collective communications on a plurality of processors that use different parallel programming paradigms, in one aspect, may comprise a schedule defining one or more tasks in a collective operation an executor that executes the task, a multisend module to perform one or more data transfer functions associated with the tasks, and a connection manager that controls one or more connections and identifies an available connection. The multisend module uses the available connection in performing the one or more data transfer functions. A plurality of processors that use different parallel programming paradigms can use a common implementation of the schedule module, the executor module, the connection manager and the multisend module via a language adaptor specific to a parallel programming paradigm implemented on a processor.
摘要翻译：在一个方面，用于在使用不同的并行编程范例的多个处理器上支持集体通信的系统和方法可以包括在集体操作中定义执行任务的执行器中的一个或多个任务的调度，执行一个执行器的多发模块或更多数据传输功能，以及连接管理器，其控制一个或多个连接并识别可用连接。多次模块在执行一个或多个数据传输功能时使用可用的连接。使用不同的并行编程范例的多个处理器可以经由特定于在处理器上实现的并行编程范例的语言适配器来使用调度模块，执行器模块，连接管理器和多发模块的通用实现。

2. 发明授权

US07984448B2 Mechanism to support generic collective communication across a variety of programming models 失效
标题翻译：支持各种编程模型中的通用集体通信的机制
公开(公告)号：US07984448B2
公开(公告)日：2011-07-19
申请号：US11768669
申请日：2007-06-26
申请人： Gheorghe Almasi , Gabor Dozsa , Sameer Kumar
发明人： Gheorghe Almasi , Gabor Dozsa , Sameer Kumar
IPC分类号： G06F9/44 , G06F9/46 , G06F15/76
CPC分类号： G06F9/54
摘要： A system and method for supporting collective communications on a plurality of processors that use different parallel programming paradigms, in one aspect, may comprise a schedule defining one or more tasks in a collective operation, an executor that executes the task, a multisend module to perform one or more data transfer functions associated with the tasks, and a connection manager that controls one or more connections and identifies an available connection. The multisend module uses the available connection in performing the one or more data transfer functions. A plurality of processors that use different parallel programming paradigms can use a common implementation of the schedule module, the executor module, the connection manager and the multisend module via a language adaptor specific to a parallel programming paradigm implemented on a processor.
摘要翻译：在一个方面，用于支持在使用不同的并行编程范例的多个处理器上的集体通信的系统和方法可以包括在集体操作中定义一个或多个任务的调度，执行该任务的执行器，执行多个模块的执行器与任务相关联的一个或多个数据传送功能，以及控制一个或多个连接并识别可用连接的连接管理器。多次模块在执行一个或多个数据传输功能时使用可用的连接。使用不同的并行编程范例的多个处理器可以经由特定于在处理器上实现的并行编程范例的语言适配器来使用调度模块，执行器模块，连接管理器和多发模块的通用实现。

3. 发明授权

US08655962B2 Shared address collectives using counter mechanisms 失效
标题翻译：共享地址集合使用计数器机制
公开(公告)号：US08655962B2
公开(公告)日：2014-02-18
申请号：US12568115
申请日：2009-09-28
申请人： Michael Blocksome , Gabor Dozsa , Thomas M. Gooding , Philip Heidelberger , Sameer Kumar , Amith R. Mamidala , Douglas Miller
发明人： Michael Blocksome , Gabor Dozsa , Thomas M. Gooding , Philip Heidelberger , Sameer Kumar , Amith R. Mamidala , Douglas Miller
IPC分类号： G06F15/16 , G06F15/167
CPC分类号： G06F9/544
摘要： A shared address space on a compute node stores data received from a network and data to transmit to the network. The shared address space includes an application buffer that can be directly operated upon by a plurality of processes, for instance, running on different cores on the compute node. A shared counter is used for one or more of signaling arrival of the data across the plurality of processes running on the compute node, signaling completion of an operation performed by one or more of the plurality of processes, obtaining reservation slots by one or more of the plurality of processes, or combinations thereof.
摘要翻译：计算节点上的共享地址空间存储从网络接收的数据和要发送到网络的数据。共享地址空间包括可以通过多个进程直接操作的应用缓冲器，例如在计算节点上的不同核上运行。共享计数器用于通过在计算节点上运行的多个进程的信令到达的一个或多个，信令完成由多个进程中的一个或多个执行的操作，通过一个或多个多个处理或其组合。

4. 发明申请

US20110078249A1 SHARED ADDRESS COLLECTIVES USING COUNTER MECHANISMS 失效
标题翻译：使用计数器机制的共享地址集合
公开(公告)号：US20110078249A1
公开(公告)日：2011-03-31
申请号：US12568115
申请日：2009-09-28
申请人： Michael Blocksome , Gabor Dozsa , Thomas M. Gooding , Philip Heidelberger , Sameer Kumar , Amith R. Mamidala , Douglas Miller
发明人： Michael Blocksome , Gabor Dozsa , Thomas M. Gooding , Philip Heidelberger , Sameer Kumar , Amith R. Mamidala , Douglas Miller
IPC分类号： G06F15/16
CPC分类号： G06F9/544
摘要： A shared address space on a compute node stores data received from a network and data to transmit to the network. The shared address space includes an application buffer that can be directly operated upon by a plurality of processes, for instance, running on different cores on the compute node. A shared counter is used for one or more of signaling arrival of the data across the plurality of processes running on the compute node, signaling completion of an operation performed by one or more of the plurality of processes, obtaining reservation slots by one or more of the plurality of processes, or combinations thereof.
摘要翻译：计算节点上的共享地址空间存储从网络接收的数据和要发送到网络的数据。共享地址空间包括可以通过多个进程直接操作的应用缓冲器，例如在计算节点上的不同核上运行。共享计数器用于通过在计算节点上运行的多个进程的信令到达的一个或多个，信令完成由多个进程中的一个或多个执行的操作，通过一个或多个多个处理或其组合。

5. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

6. 发明申请

US20100268852A1 Replenishing Data Descriptors in a DMA Injection FIFO Buffer 失效
标题翻译：在DMA注入FIFO缓冲区中补充数据描述符
公开(公告)号：US20100268852A1
公开(公告)日：2010-10-21
申请号：US11755501
申请日：2007-05-30
申请人： Charles J Archer , Michael A. Blocksome , Bob R. Cernohous , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
发明人： Charles J Archer , Michael A. Blocksome , Bob R. Cernohous , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Methods, apparatus, and products are disclosed for replenishing data descriptors in a Direct Memory Access (‘DMA’) injection first-in-first-out (‘FIFO’) buffer that include: determining, by a messaging module on an origin compute node, whether a number of data descriptors in a DMA injection FIFO buffer exceeds a predetermined threshold, each data descriptor specifying an application message for transmission to a target compute node; queuing, by the messaging module, a plurality of new data descriptors in a pending descriptor queue if the number of the data descriptors in the DMA injection FIFO buffer exceeds the predetermined threshold; establishing, by the messaging module, interrupt criteria that specify when to replenish the injection FIFO buffer with the plurality of new data descriptors in the pending descriptor queue; and injecting, by the messaging module, the plurality of new data descriptors into the injection FIFO buffer in dependence upon the interrupt criteria.
摘要翻译：公开了用于在直接存储器访问（“DMA”）注入先进先出（'FIFO'）缓冲器中补充数据描述符的方法，装置和产品，其包括：由原始计算节点无论DMA注入FIFO缓冲器中的多个数据描述符是否超过预定阈值，每个数据描述符指定用于传输到目标计算节点的应用消息; 如果DMA注入FIFO缓冲器中的数据描述符的数量超过预定阈值，则由消息接发模块排队等待描述符队列中的多个新数据描述符; 由所述消息传递模块建立中断标准，所述中断标准指定何时用所述待处理描述符队列中的所述多个新数据描述符补充所述注入FIFO缓冲器; 以及根据所述中断标准，由所述消息收发模块将所述多个新数据描述符注入到所述注入FIFO缓冲器中。

7. 发明授权

US08543722B2 Message passing with queues and channels 失效
标题翻译：消息传递与队列和通道
公开(公告)号：US08543722B2
公开(公告)日：2013-09-24
申请号：US12750363
申请日：2010-03-30
申请人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow , Robert W. Wisniewski
发明人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow , Robert W. Wisniewski
IPC分类号： G06F15/16
CPC分类号： G06F9/546
摘要： In an embodiment, a send thread receives an identifier that identifies a destination node and a pointer to data. The send thread creates a first send request in response to the receipt of the identifier and the data pointer. The send thread selects a selected channel from among a plurality of channels. The selected channel comprises a selected hand-off queue and an identification of a selected message unit. Each of the channels identifies a different message unit. The selected hand-off queue is randomly accessible. If the selected hand-off queue contains an available entry, the send thread adds the first send request to the selected hand-off queue. If the selected hand-off queue does not contain an available entry, the send thread removes a second send request from the selected hand-off queue and sends the second send request to the selected message unit.
摘要翻译：在一个实施例中，发送线程接收标识目的地节点的标识符和指向数据的指针。响应于接收到标识符和数据指针，发送线程创建第一个发送请求。发送线程从多个信道中选择所选择的信道。所选择的信道包括所选择的切换队列和所选择的消息单元的标识。每个通道标识不同的消息单元。所选择的切换队列是随机访问的。如果所选择的切换队列包含可用条目，则发送线程将第一个发送请求添加到所选择的切换队列。如果所选择的切换队列不包含可用条目，则发送线程从所选择的切换队列中移除第二发送请求，并将第二发送请求发送到所选择的消息单元。

8. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

9. 发明申请

US20110179229A1 STORE-OPERATE-COHERENCE-ON-VALUE 有权
标题翻译：存储操作相关值
公开(公告)号：US20110179229A1
公开(公告)日：2011-07-21
申请号：US12986652
申请日：2011-01-07
申请人： Dong Chen , Philip Heidelberger , Sameer Kumar , Martin Ohmacht , Burkhard Steinmacher-Burow
发明人： Dong Chen , Philip Heidelberger , Sameer Kumar , Martin Ohmacht , Burkhard Steinmacher-Burow
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/3834 , Y02D10/13
摘要： A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.
摘要翻译：一种用于在包括多个处理器和至少一个高速缓冲存储器设备的并行计算环境中执行各种存储操作指令的系统，方法和计算机程序产品。系统中的队列从处理器接收存储操作指令，该指令指定在哪个条件下调用高速缓存一致性操作。系统中的硬件单元运行接收到的存储操作指令。硬件单元评估运行接收到的存储操作指令的结果是否满足条件。如果结果满足条件，则硬件单元调用与接收到的存储操作指令相关联的高速缓存存储器地址的高速缓存一致性操作。否则，硬件单元不会调用高速缓存存储器设备上的高速缓存一致性操作。

10. 发明授权

US07899055B2 Method for route optimization with dual mobile IPv4 node in IPv6-only network 有权
标题翻译：仅在IPv6网络中使用双移动IPv4节点进行路由优化的方法
公开(公告)号：US07899055B2
公开(公告)日：2011-03-01
申请号：US11645671
申请日：2006-12-27
申请人： Kishore Mundra , Lakshmi Praba Gurusamy , Sameer Kumar , Ranjitsinh Udaysinh Wable
发明人： Kishore Mundra , Lakshmi Praba Gurusamy , Sameer Kumar , Ranjitsinh Udaysinh Wable
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04W8/082 , H04W80/04 , H04W80/045
摘要： A method for route optimization with a dual mobile IPv4 node in an IPv6-only network is provided. The method includes the operations of: receiving a visited IPv6 address from a router when the dual mobile node is connected to the IPv6-only network; updating a home agent with the IPv6 address; deregistering a binding update with a correspondent node via the home agent; updating the correspondent node with an IPv6 address; checking the reachability of packets directly to the correspondent node using its IPv6 address; the mobile node starting sending, to the CN, data packets tunneled in an IPv6 packet once the reachability is verified; and the correspondent node sending tunneled data packets directly to an IPv6 address of the mobile node.
摘要翻译：提供了一种仅在IPv6网络中使用双移动IPv4节点进行路由优化的方法。该方法包括以下操作：当双移动节点连接到仅IPv6网络时，从路由器接收到访问的IPv6地址; 使用IPv6地址更新归属代理; 通过归属代理注销与通信节点的绑定更新; 用IPv6地址更新对端节点; 使用其IPv6地址将数据包的可达性直接检查到对端节点; 移动节点开始向CN发送一旦IPv6包中隧道的数据包，一旦可达性得到验证，并且对端节点将隧道化数据分组直接发送到移动节点的IPv6地址。

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