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1. 发明申请

US20100268852A1 Replenishing Data Descriptors in a DMA Injection FIFO Buffer 失效
标题翻译：在DMA注入FIFO缓冲区中补充数据描述符
公开(公告)号：US20100268852A1
公开(公告)日：2010-10-21
申请号：US11755501
申请日：2007-05-30
申请人： Charles J Archer , Michael A. Blocksome , Bob R. Cernohous , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
发明人： Charles J Archer , Michael A. Blocksome , Bob R. Cernohous , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Methods, apparatus, and products are disclosed for replenishing data descriptors in a Direct Memory Access (‘DMA’) injection first-in-first-out (‘FIFO’) buffer that include: determining, by a messaging module on an origin compute node, whether a number of data descriptors in a DMA injection FIFO buffer exceeds a predetermined threshold, each data descriptor specifying an application message for transmission to a target compute node; queuing, by the messaging module, a plurality of new data descriptors in a pending descriptor queue if the number of the data descriptors in the DMA injection FIFO buffer exceeds the predetermined threshold; establishing, by the messaging module, interrupt criteria that specify when to replenish the injection FIFO buffer with the plurality of new data descriptors in the pending descriptor queue; and injecting, by the messaging module, the plurality of new data descriptors into the injection FIFO buffer in dependence upon the interrupt criteria.
摘要翻译：公开了用于在直接存储器访问（“DMA”）注入先进先出（'FIFO'）缓冲器中补充数据描述符的方法，装置和产品，其包括：由原始计算节点无论DMA注入FIFO缓冲器中的多个数据描述符是否超过预定阈值，每个数据描述符指定用于传输到目标计算节点的应用消息; 如果DMA注入FIFO缓冲器中的数据描述符的数量超过预定阈值，则由消息接发模块排队等待描述符队列中的多个新数据描述符; 由所述消息传递模块建立中断标准，所述中断标准指定何时用所述待处理描述符队列中的所述多个新数据描述符补充所述注入FIFO缓冲器; 以及根据所述中断标准，由所述消息收发模块将所述多个新数据描述符注入到所述注入FIFO缓冲器中。

2. 发明授权

US08037213B2 Replenishing data descriptors in a DMA injection FIFO buffer 失效
标题翻译：在DMA注入FIFO缓冲区中补充数据描述符
公开(公告)号：US08037213B2
公开(公告)日：2011-10-11
申请号：US11755501
申请日：2007-05-30
申请人： Charles J. Archer , Michael A. Blocksome , Bob R. Cernohous , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
发明人： Charles J. Archer , Michael A. Blocksome , Bob R. Cernohous , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
IPC分类号： G06F3/00 , H04L12/28
CPC分类号： G06F13/28
摘要： Methods, apparatus, and products are disclosed for replenishing data descriptors in a Direct Memory Access (‘DMA’) injection first-in-first-out (‘FIFO’) buffer that include: determining, by a messaging module on an origin compute node, whether a number of data descriptors in a DMA injection FIFO buffer exceeds a predetermined threshold, each data descriptor specifying an application message for transmission to a target compute node; queuing, by the messaging module, a plurality of new data descriptors in a pending descriptor queue if the number of the data descriptors in the DMA injection FIFO buffer exceeds the predetermined threshold; establishing, by the messaging module, interrupt criteria that specify when to replenish the injection FIFO buffer with the plurality of new data descriptors in the pending descriptor queue; and injecting, by the messaging module, the plurality of new data descriptors into the injection FIFO buffer in dependence upon the interrupt criteria.
摘要翻译：公开了用于在直接存储器访问（“DMA”）注入先进先出（'FIFO'）缓冲器中补充数据描述符的方法，装置和产品，其包括：由原始计算节点无论DMA注入FIFO缓冲器中的多个数据描述符是否超过预定阈值，每个数据描述符指定用于传输到目标计算节点的应用消息; 如果DMA注入FIFO缓冲器中的数据描述符的数量超过预定阈值，则由消息接发模块排队等待描述符队列中的多个新数据描述符; 由所述消息传递模块建立中断标准，所述中断标准指定何时用所述待处理描述符队列中的所述多个新数据描述符补充所述注入FIFO缓冲器; 以及根据所述中断标准，由所述消息收发模块将所述多个新数据描述符注入到所述注入FIFO缓冲器中。

3. 发明授权

US07958274B2 Heuristic status polling 有权
标题翻译：启发式状态轮询
公开(公告)号：US07958274B2
公开(公告)日：2011-06-07
申请号：US11764282
申请日：2007-06-18
申请人： Charles J. Archer , Michael A. Blocksome , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Joseph D. Ratterman
发明人： Charles J. Archer , Michael A. Blocksome , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Joseph D. Ratterman
IPC分类号： G06F3/00
CPC分类号： H04L12/44 , H04L12/403
摘要： Methods, compute nodes, and computer program products are provided for heuristic status polling of a component in a computing system. Embodiments include receiving, by a polling module from a requesting application, a status request requesting status of a component; determining, by the polling module, whether an activity history for the component satisfies heuristic polling criteria; polling, by the polling module, the component for status if the activity history for the component satisfies the heuristic polling criteria; and not polling, by the polling module, the component for status if the activity history for the component does not satisfy the heuristic criteria.
摘要翻译：提供方法，计算节点和计算机程序产品用于计算系统中组件的启发状态轮询。实施例包括通过轮询模块从请求应用程序接收请求状态的组件的状态请求; 由轮询模块确定该组件的活动历史是否满足启发式轮询标准; 如果组件的活动历史满足启发式轮询标准，轮询由轮询模块组成状态; 如果组件的活动历史不满足启发式标准，则轮询模块不会轮询该组件的状态。

4. 发明申请

US20080313376A1 Heuristic Status Polling 有权
标题翻译：启发式状态轮询
公开(公告)号：US20080313376A1
公开(公告)日：2008-12-18
申请号：US11764282
申请日：2007-06-18
申请人： Charles J. Archer , Michael A. Blocksome , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Joseph D. Ratterman
发明人： Charles J. Archer , Michael A. Blocksome , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Joseph D. Ratterman
IPC分类号： G06F13/22
CPC分类号： H04L12/44 , H04L12/403
摘要： Methods, compute nodes, and computer program products are provided for heuristic status polling of a component in a computing system. Embodiments include receiving, by a polling module from a requesting application, a status request requesting status of a component; determining, by the polling module, whether an activity history for the component satisfies heuristic polling criteria; polling, by the polling module, the component for status if the activity history for the component satisfies the heuristic polling criteria; and not polling, by the polling module, the component for status if the activity history for the component does not satisfy the heuristic criteria.
摘要翻译：提供方法，计算节点和计算机程序产品用于计算系统中组件的启发状态轮询。实施例包括通过轮询模块从请求应用程序接收请求状态的组件的状态请求; 由轮询模块确定该组件的活动历史是否满足启发式轮询标准; 如果组件的活动历史满足启发式轮询标准，轮询由轮询模块组成状态; 如果组件的活动历史不满足启发式标准，则轮询模块不会轮询该组件的状态。

5. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

6. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

7. 发明授权

US07890597B2 Direct memory access transfer completion notification 失效
标题翻译：直接内存访问传输完成通知
公开(公告)号：US07890597B2
公开(公告)日：2011-02-15
申请号：US11829317
申请日：2007-07-27
申请人： Charles J. Archer , Michael A. Blocksome , Jeffrey J. Parker
发明人： Charles J. Archer , Michael A. Blocksome , Jeffrey J. Parker
IPC分类号： G06F15/167
CPC分类号： G06F9/544
摘要： Methods, systems, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA on an origin node in an origin injection FIFO, a data descriptor for an application message; inserting, by the origin DMA, a reflection descriptor in the origin injection FIFO, the reflection descriptor specifying a remote get operation for injecting a completion notification descriptor in a reflection injection FIFO on a reflection node; transferring, by the origin DMA to a target node, the message in dependence upon the data descriptor; in response to completing the message transfer, transferring, by the origin DMA to the reflection node, the completion notification descriptor in dependence upon the reflection descriptor; receiving, by the origin DMA from the reflection node, a completion packet; and notifying, by the origin DMA in response to receiving the completion packet, the origin node's processing core that the message transfer is complete.
摘要翻译：公开了用于DMA传输完成通知的方法，系统和产品，其包括：通过原始注入FIFO中的原始节点上的原始DMA插入应用消息的数据描述符; 由原点DMA插入原始注入FIFO中的反射描述符，反射描述符指定用于在反射节点上的反射注入FIFO中注入完成通知描述符的远程获取操作; 根据数据描述符将原始DMA传送到目标节点消息; 响应于完成消息传送，根据反射描述符将源DMA传送到反射节点，完成通知描述符; 通过来自反射节点的原点DMA接收完成分组; 并且由原始DMA响应于接收完成分组通知消息传送完成的原始节点的处理核心。

8. 发明授权

US07779173B2 Direct memory access transfer completion notification 有权
标题翻译：直接内存访问传输完成通知
公开(公告)号：US07779173B2
公开(公告)日：2010-08-17
申请号：US11754719
申请日：2007-05-29
申请人： Charles J. Archer , Michael A. Blocksome , Jeffrey J. Parker
发明人： Charles J. Archer , Michael A. Blocksome , Jeffrey J. Parker
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： Methods, apparatus, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA engine on an origin compute node in an injection FIFO buffer, a data descriptor for an application message to be transferred to a target compute node on behalf of an application on the origin compute node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying an address of a completion notification field in application storage for the application; transferring, by the origin DMA engine to the target compute node, the message in dependence upon the data descriptor; and notifying, by the origin DMA engine, the application that the transfer of the message is complete, including performing a local direct put operation to store predesignated notification data at the address of the completion notification field.
摘要翻译：公开了用于DMA传输完成通知的方法，装置和产品，其包括：通过在注入FIFO缓冲器中的原始计算节点上的原始DMA引擎将要传送到目标计算节点的应用消息的数据描述符代表原始计算节点上的应用程序; 由原始DMA引擎在消息的数据描述符之后插入注入FIFO缓冲器中的完成通知描述符，完成通知描述符指定应用程序的应用程序存储中的完成通知字段的地址; 根据数据描述符将原始DMA引擎传送到目标计算节点消息; 并且由原始DMA引擎通知消息传送完成的应用，包括执行本地直接放置操作以将预定指定的通知数据存储在完成通知字段的地址处。

9. 发明授权

US08732725B2 Managing internode data communications for an uninitialized process in a parallel computer 有权
标题翻译：管理并行计算机中未初始化进程的节点间数据通信
公开(公告)号：US08732725B2
公开(公告)日：2014-05-20
申请号：US13292293
申请日：2011-11-09
申请人： Charles J. Archer , Michael A. Blocksome , Douglas R. Miller , Jeffrey J. Parker , Joseph D. Ratterman , Brian E. Smith
发明人： Charles J. Archer , Michael A. Blocksome , Douglas R. Miller , Jeffrey J. Parker , Joseph D. Ratterman , Brian E. Smith
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F15/167 , G06F9/544 , G06F15/17318
摘要： A parallel computer includes nodes, each having main memory and a messaging unit (MU). Each MU includes computer memory, which in turn includes, MU message buffers. Each MU message buffer is associated with an uninitialized process on the compute node. In the parallel computer, managing internode data communications for an uninitialized process includes: receiving, by an MU of a compute node, one or more data communications messages in an MU message buffer associated with an uninitialized process on the compute node; determining, by an application agent, that the MU message buffer associated with the uninitialized process is full prior to initialization of the uninitialized process; establishing, by the application agent, a temporary message buffer for the uninitialized process in main computer memory; and moving, by the application agent, data communications messages from the MU message buffer associated with the uninitialized process to the temporary message buffer in main computer memory.
摘要翻译：并行计算机包括各自具有主存储器和消息传送单元（MU）的节点。每个MU包括计算机存储器，其又包括MU消息缓冲器。每个MU消息缓冲区与计算节点上的未初始化进程相关联。在并行计算机中，管理未初始化过程的节点间数据通信包括：由计算节点的MU接收与计算节点上的未初始化过程相关联的MU消息缓冲器中的一个或多个数据通信消息; 由应用代理确定与未初始化过程相关联的MU消息缓冲器在未初始化过程的初始化之前已满; 由应用代理建立用于主计算机存储器中未初始化过程的临时消息缓冲器; 并且由应用代理将与未初始化过程相关联的MU消息缓冲器的数据通信消息移动到主计算机存储器中的临时消息缓冲器。

10. 发明申请

US20130117764A1 Internode Data Communications In A Parallel Computer 失效
标题翻译：并行计算机中的国际数据通信
公开(公告)号：US20130117764A1
公开(公告)日：2013-05-09
申请号：US13290642
申请日：2011-11-07
申请人： Charles J. Archer , Michael A. Blocksome , Douglas R. Miller , Jeffrey J. Parker , Joseph D. Ratterman , Brian E. Smith
发明人： Charles J. Archer , Michael A. Blocksome , Douglas R. Miller , Jeffrey J. Parker , Joseph D. Ratterman , Brian E. Smith
IPC分类号： G06F9/46
CPC分类号： G06F9/544
摘要： Internode data communications in a parallel computer that includes compute nodes that each include main memory and a messaging unit, the messaging unit including computer memory and coupling compute nodes for data communications, in which, for each compute node at compute node boot time: a messaging unit allocates, in the messaging unit's computer memory, a predefined number of message buffers, each message buffer associated with a process to be initialized on the compute node; receives, prior to initialization of a particular process on the compute node, a data communications message intended for the particular process; and stores the data communications message in the message buffer associated with the particular process. Upon initialization of the particular process, the process establishes a messaging buffer in main memory of the compute node and copies the data communications message from the message buffer of the messaging unit into the message buffer of main memory.
摘要翻译：并行计算机中的国际数据通信包括计算节点，每个计算节点包括主存储器和消息传送单元，消息传送单元包括计算机存储器和耦合用于数据通信的计算节点，其中针对计算节点启动时的每个计算节点：消息单元在消息接发单元的计算机存储器中分配预定数量的消息缓冲器，每个消息缓冲器与在计算节点上被初始化的进程相关联; 在计算节点上的特定进程的初始化之前接收用于该特定进程的数据通信消息; 并将数据通信消息存储在与特定进程相关联的消息缓冲器中。在特定进程的初始化时，该过程在计算节点的主存储器中建立消息缓存器，并将数据通信消息从消息传送单元的消息缓冲器复制到主存储器的消息缓冲器中。

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