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1. 发明申请

US20080318381A1 METHODS OF FORMING HIGH DENSITY SEMICONDUCTOR DEVICES USING RECURSIVE SPACER TECHNIQUE 有权
标题翻译：使用回放间隔技术形成高密度半导体器件的方法
公开(公告)号：US20080318381A1
公开(公告)日：2008-12-25
申请号：US11765866
申请日：2007-06-20
申请人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
发明人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.
摘要翻译：公开了高密度半导体器件及其制造方法。利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其可以小于所使用的工艺的最小可光刻解析的元件尺寸。可以处理第一组间隔件以提供平面和平行的侧壁。可以在第一组间隔件的平面和平行的侧壁上形成第二组间隔件。第二组间隔件用作掩模以在第二组间隔物下方的层中形成一个或多个电路元件。根据本发明的实施例的步骤允许使用递归间隔物技术，其产生要形成的坚固的，均匀间隔的间隔物并用作电路元件的掩模。

2. 发明授权

US08143156B2 Methods of forming high density semiconductor devices using recursive spacer technique 有权
标题翻译：使用递归间隔技术形成高密度半导体器件的方法
公开(公告)号：US08143156B2
公开(公告)日：2012-03-27
申请号：US11765866
申请日：2007-06-20
申请人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
发明人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.
摘要翻译：公开了高密度半导体器件及其制造方法。利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其可以小于所使用的工艺的最小可光刻解析的元件尺寸。可以处理第一组间隔件以提供平面和平行的侧壁。可以在第一组间隔件的平面和平行的侧壁上形成第二组间隔件。第二组间隔件用作掩模以在第二组间隔物下方的层中形成一个或多个电路元件。根据本发明的实施例的步骤允许使用递归间隔物技术，其产生要形成的坚固的，均匀间隔的间隔物并用作电路元件的掩模。

3. 发明授权

US08097498B2 Damascene method of making a nonvolatile memory device 有权
公开(公告)号：US08097498B2
公开(公告)日：2012-01-17
申请号：US12693322
申请日：2010-01-25
申请人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
发明人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.

4. 发明授权

US07915664B2 Non-volatile memory with sidewall channels and raised source/drain regions 有权
标题翻译：具有侧壁通道和升高的源极/漏极区域的非易失性存储器
公开(公告)号：US07915664B2
公开(公告)日：2011-03-29
申请号：US12105242
申请日：2008-04-17
申请人： Henry Chien , Takashi Orimoto , George Matamis , James Kai , Vinod R. Purayath
发明人： Henry Chien , Takashi Orimoto , George Matamis , James Kai , Vinod R. Purayath
IPC分类号： H01L29/788
CPC分类号： G11C8/10 , G11C8/04 , G11C11/5621 , G11C16/0483 , G11C19/00 , H01L21/28273 , H01L27/11521
摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.
摘要翻译：一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。浮动门可以具有均匀的宽度或倒T形。凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为减少侧壁绝缘层与底部绝缘层的厚度的比例可以为约0.3至0.67。

5. 发明授权

US07807529B2 Lithographically space-defined charge storage regions in non-volatile memory 有权
标题翻译：非易失性存储器中的光刻空间定义电荷存储区域
公开(公告)号：US07807529B2
公开(公告)日：2010-10-05
申请号：US11960513
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions.
摘要翻译：在制造基于半导体的存储器件期间，使用光刻定义的间距来定义特征尺寸。牺牲特征以具有由光刻图案限定的线尺寸和空间尺寸的指定间距在衬底上形成。用于存储元件的电荷存储区域使用光刻定义的间隔在相邻的牺牲特征之间的空间中形成，以将电荷存储区域的栅极长度或尺寸固定在列方向上。可以使用指定间距处的不等的线和空间尺寸来形成小于与光刻工艺相关联的最小可解析特征尺寸的特征尺寸。较大的线尺寸可以改善线边缘粗糙度，同时减小电荷存储区域在列方向上的尺寸。存储元件的附加电荷存储区域可以形成在如此限定的电荷存储区域上，例如通过沉积和蚀刻第二电荷存储层以形成具有小于栅极长度的列方向尺寸的第二电荷存储区域的第一电荷存储区域。

6. 发明授权

US07736973B2 Non-volatile memory arrays having dual control gate cell structures and a thick control gate dielectric and methods of forming 有权
标题翻译：具有双控制栅极单元结构的非易失性存储器阵列和厚控制栅极电介质以及形成方法
公开(公告)号：US07736973B2
公开(公告)日：2010-06-15
申请号：US12020428
申请日：2008-01-25
申请人： Takashi Orimoto , George Matamis , James Kai
发明人： Takashi Orimoto , George Matamis , James Kai
IPC分类号： H01L21/3205
CPC分类号： H01L27/11521 , H01L27/11519
摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming are provided. A charge storage layer is etched into strips extending across a substrate surface in a row direction with a tunnel dielectric layer therebetween. The resulting strips may be continuous in the row direction or may comprise individual charge storage regions if already divided along their length in the row direction. A second layer of dielectric material is formed along the sidewalls of the strips and over the tunnel dielectric layer in the spaces therebetween. The second layer is etched into regions overlaying the tunnel dielectric layer in the spaces between strips. An intermediate dielectric layer is formed along exposed portions of the sidewalls of the strips and over the second dielectric layer in the spaces therebetween. A layer of control gate material is deposited in the spaces between strips. The resulting control gates are separated from the strips by the intermediate dielectric layer and from the substrate surface by the tunnel dielectric layer, the second layer of dielectric material and the intermediate dielectric layer.
摘要翻译：提供了具有双控制栅极存储单元的非易失性半导体存储器件和形成方法。电荷存储层被蚀刻成沿着行方向延伸穿过衬底表面的条带，其间具有隧道介电层。所得到的条带可以在行方向上是连续的，或者可以包括单独的电荷存储区域，如果沿着它们的行方向上的长度被划分。第二层电介质材料沿着条的侧壁和隧道介电层之间的空间形成。第二层被蚀刻到条带之间的空间中覆盖隧道介电层的区域中。沿着条的侧壁的暴露部分和在它们之间的空间中的第二介电层上方形成中间介电层。控制栅极材料层沉积在条带之间的空间中。所得到的控制栅极通过中间介电层和通过隧道介电层，第二介电材料层和中间介质层从衬底表面与条分离。

7. 发明申请

US20100055889A1 Composite Charge Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies 有权
标题翻译：使用蚀刻停止技术在非易失性存储器中的复合电荷存储结构形成
公开(公告)号：US20100055889A1
公开(公告)日：2010-03-04
申请号：US12615154
申请日：2009-11-09
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/28
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.
摘要翻译：包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。可以增加各个存储单元尺寸的一致性。

8. 发明申请

US20080248621A1 Integrated Non-Volatile Memory And Peripheral Circuitry Fabrication 有权
标题翻译：集成非易失性存储器和外围电路制造
公开(公告)号：US20080248621A1
公开(公告)日：2008-10-09
申请号：US12058512
申请日：2008-03-28
申请人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
发明人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
IPC分类号： H01L21/336
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供非易失性存储器和集成存储器和外围电路制造工艺。使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。中间电介质层设置在电荷存储区域的上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

9. 发明授权

US08546152B2 Enhanced endpoint detection in non-volatile memory fabrication processes 有权
标题翻译：在非易失性存储器制造过程中增强端点检测
公开(公告)号：US08546152B2
公开(公告)日：2013-10-01
申请号：US11960485
申请日：2007-12-19
申请人： Takashi Orimoto , George Matamis , James Kai , Vinod Robert Purayath
发明人： Takashi Orimoto , George Matamis , James Kai , Vinod Robert Purayath
IPC分类号： H01L21/66
CPC分类号： H01L22/26 , H01L27/11521
摘要： A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete.
摘要翻译：提供一种制造非易失性存储器的方法，用于采用具有多个电荷存储区域的电荷存储元件的存储单元。第一电荷存储层在半导体衬底的存储器阵列区域和端点区域的隧道电介质层上形成。从端点区域去除第一电荷存储层以暴露隧道电介质区域。第二电荷存储层形成在存储器阵列区域的第一电荷存储层上，并在端点区域的隧道电介质层上形成。当蚀刻第二电荷存储层以形成存储器单元的干区域时，隧道介电层提供可检测的端点信号，以指示第二电荷存储层的蚀刻完成。

10. 发明授权

US08263465B2 Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer 有权
标题翻译：使用耦合层的包括自对准金属纳米点的浮栅形成存储器的方法
公开(公告)号：US08263465B2
公开(公告)日：2012-09-11
申请号：US12754408
申请日：2010-04-05
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
IPC分类号： H01L21/339
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译：提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

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