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1. 发明申请

US20080318381A1 METHODS OF FORMING HIGH DENSITY SEMICONDUCTOR DEVICES USING RECURSIVE SPACER TECHNIQUE 有权
标题翻译：使用回放间隔技术形成高密度半导体器件的方法
公开(公告)号：US20080318381A1
公开(公告)日：2008-12-25
申请号：US11765866
申请日：2007-06-20
申请人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
发明人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.
摘要翻译：公开了高密度半导体器件及其制造方法。利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其可以小于所使用的工艺的最小可光刻解析的元件尺寸。可以处理第一组间隔件以提供平面和平行的侧壁。可以在第一组间隔件的平面和平行的侧壁上形成第二组间隔件。第二组间隔件用作掩模以在第二组间隔物下方的层中形成一个或多个电路元件。根据本发明的实施例的步骤允许使用递归间隔物技术，其产生要形成的坚固的，均匀间隔的间隔物并用作电路元件的掩模。

2. 发明授权

US08143156B2 Methods of forming high density semiconductor devices using recursive spacer technique 有权
标题翻译：使用递归间隔技术形成高密度半导体器件的方法
公开(公告)号：US08143156B2
公开(公告)日：2012-03-27
申请号：US11765866
申请日：2007-06-20
申请人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
发明人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.
摘要翻译：公开了高密度半导体器件及其制造方法。利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其可以小于所使用的工艺的最小可光刻解析的元件尺寸。可以处理第一组间隔件以提供平面和平行的侧壁。可以在第一组间隔件的平面和平行的侧壁上形成第二组间隔件。第二组间隔件用作掩模以在第二组间隔物下方的层中形成一个或多个电路元件。根据本发明的实施例的步骤允许使用递归间隔物技术，其产生要形成的坚固的，均匀间隔的间隔物并用作电路元件的掩模。

3. 发明授权

US07615445B2 Methods of reducing coupling between floating gates in nonvolatile memory 有权
标题翻译：减少非易失性存储器中浮动栅极耦合的方法
公开(公告)号：US07615445B2
公开(公告)日：2009-11-10
申请号：US11534135
申请日：2006-09-21
申请人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
发明人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。具有倒T形浮置栅极的阵列可以以自对准的方式形成。

4. 发明申请

US20080074920A1 Nonvolatile Memory with Reduced Coupling Between Floating Gates 审中-公开
标题翻译：浮动闸门耦合减少的非易失性存储器
公开(公告)号：US20080074920A1
公开(公告)日：2008-03-27
申请号：US11534139
申请日：2006-09-21
申请人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
发明人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
IPC分类号： G11C5/06
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。具有倒T形浮置栅极的阵列可以以自对准的方式形成。

5. 发明申请

US20100047979A1 METHOD OF REDUCING COUPLING BETWEEN FLOATING GATES IN NONVOLATILE MEMORY 有权
标题翻译：降低非易失性存储器中浮动栅之间耦合的方法
公开(公告)号：US20100047979A1
公开(公告)日：2010-02-25
申请号：US12567257
申请日：2009-09-25
申请人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
发明人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
IPC分类号： H01L21/336 , H01L21/76 , H01L21/3205
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。

6. 发明申请

US20130105881A1 Self-Aligned Planar Flash Memory And Methods Of Fabrication 审中-公开
标题翻译：自对平面闪存及其制作方法
公开(公告)号：US20130105881A1
公开(公告)日：2013-05-02
申请号：US13646500
申请日：2012-10-05
申请人： James K. Kai , Vinod R. Purayath , George Matamis , Nima Mokhlesi , Cuong Trinh
发明人： James K. Kai , Vinod R. Purayath , George Matamis , Nima Mokhlesi , Cuong Trinh
IPC分类号： H01L29/788 , H01L21/762 , H01L21/336
CPC分类号： H01L27/11519 , H01L27/11524 , H01L29/42332 , H01L29/66825
摘要： A non-volatile memory fabrication process includes the formation of a complete memory cell layer stack before isolation region formation. The memory cell layer stack includes an additional place holding control gate layer. After forming the layer stack columns, the additional control gate layer will be incorporated between an overlying control gate layer and underlying intermediate dielectric layer. The additional control gate layer is self-aligned to isolation regions between columns while the overlying control gate layer is etched into lines for contact to the additional control gate layer. In one embodiment, the placeholder control gate layer facilitates a contact point to the overlying control gate layer such that contact between the control gate layers and the charge storage layer is not required for select gate formation.
摘要翻译：非易失性存储器制造工艺包括在形成隔离区之前形成完整的存储单元层堆叠。存储单元层堆叠包括附加位置保持控制栅层。在形成层堆叠列之后，附加的控制栅层将被并入在覆盖的控制栅极层和下面的中间介质层之间。附加控制栅极层与柱之间的隔离区域自对准，同时将覆盖的控制栅极层蚀刻成用于与附加控制栅极层接触的线。在一个实施例中，占位符控制栅极层有助于与上覆控制栅极层的接触点，使得选择栅极形成不需要控制栅极层与电荷存储层之间的接触。

7. 发明申请

US20110111583A1 METHOD OF REDUCING COUPLING BETWEEN FLOATING GATES IN NONVOLATILE MEMORY 有权
标题翻译：降低非易失性存储器中浮动栅之间耦合的方法
公开(公告)号：US20110111583A1
公开(公告)日：2011-05-12
申请号：US13010563
申请日：2011-01-20
申请人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
发明人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。

8. 发明授权

US08288225B2 Method of reducing coupling between floating gates in nonvolatile memory 有权
标题翻译：减少非易失性存储器中浮动栅极耦合的方法
公开(公告)号：US08288225B2
公开(公告)日：2012-10-16
申请号：US13010563
申请日：2011-01-20
申请人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
发明人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。

9. 发明授权

US07910434B2 Method of reducing coupling between floating gates in nonvolatile memory 有权
标题翻译：减少非易失性存储器中浮动栅极耦合的方法
公开(公告)号：US07910434B2
公开(公告)日：2011-03-22
申请号：US12567257
申请日：2009-09-25
申请人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
发明人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。

10. 发明申请

US20080076217A1 Methods of Reducing Coupling Between Floating Gates in Nonvolatile Memory 有权
标题翻译：减少非易失性存储器中浮动栅极耦合的方法
公开(公告)号：US20080076217A1
公开(公告)日：2008-03-27
申请号：US11534135
申请日：2006-09-21
申请人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
发明人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。具有倒T形浮置栅极的阵列可以以自对准的方式形成。

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