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1. 发明申请

US20100310030A1 PHASE LOCKED LOOP DEVICE AND METHOD THEREOF 有权
标题翻译：相位锁定环路装置及其方法
公开(公告)号：US20100310030A1
公开(公告)日：2010-12-09
申请号：US12480344
申请日：2009-06-08
申请人： Gayathri A. Bhagavatheeswaran , Joseph P. Gergen , Arvind Raman , Hector Sanchez
发明人： Gayathri A. Bhagavatheeswaran , Joseph P. Gergen , Arvind Raman , Hector Sanchez
IPC分类号： H03D3/24
CPC分类号： H03D13/00 , G11C7/222 , G11C29/1201 , H03L7/0805
摘要： A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, in indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.
摘要翻译：锁相环装置包括相位检测器，该相位检测器测量参考时钟信号和提供给器件模块的输出时钟信号之间的相位差。相位检测器提供具有指示相位差的宽度的脉冲。如果相位差超过多个阈值中的一个，则可以确定in指示符。基于指示器，控制模块可以采取补救措施，例如向设备模块提供不同的时钟信号或在处理器设备触发中断。

2. 发明授权

US08509370B2 Phase locked loop device and method thereof 有权
标题翻译：锁相环装置及其方法
公开(公告)号：US08509370B2
公开(公告)日：2013-08-13
申请号：US12480344
申请日：2009-06-08
申请人： Gayathri A. Bhagavatheeswaran , Joseph P. Gergen , Arvind Raman , Hector Sanchez
发明人： Gayathri A. Bhagavatheeswaran , Joseph P. Gergen , Arvind Raman , Hector Sanchez
IPC分类号： H03D3/24
CPC分类号： H03D13/00 , G11C7/222 , G11C29/1201 , H03L7/0805
摘要： A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, an indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.
摘要翻译：锁相环装置包括相位检测器，该相位检测器测量参考时钟信号和提供给器件模块的输出时钟信号之间的相位差。相位检测器提供具有指示相位差的宽度的脉冲。如果相位差超过多个阈值中的一个，则可以断言指示符。基于指示器，控制模块可以采取补救措施，例如向设备模块提供不同的时钟信号或在处理器设备触发中断。

3. 发明申请

US20150268711A1 Selecting A Low Power State Based On Cache Flush Latency Determination 有权
标题翻译：基于缓存冲突延迟确定选择低功耗状态
公开(公告)号：US20150268711A1
公开(公告)日：2015-09-24
申请号：US14221696
申请日：2014-03-21
申请人： Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
发明人： Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/3296 , G06F12/0804 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/084 , G06F12/128 , G06F2212/1028 , G06F2212/314 , G06F2212/621 , G06F2212/69 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/152 , Y02D10/172 , Y02D50/20
摘要： In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核以独立地执行指令，耦合到核的共享高速缓存并且包括多条线来存储数据，以及包括低功率控制逻辑的功率控制器来计算冲洗等待时间所述共享高速缓存基于所述多条线路的状态。描述和要求保护其他实施例。

4. 发明申请

US20090150843A1 METHOD AND APPARATUS FOR MAKING A SEMICONDUCTOR DEVICE USING HARDWARE DESCRIPTION HAVING MERGED FUNCTIONAL AND TEST LOGIC BLOCKS 有权
标题翻译：使用具有合并功能和测试逻辑块的硬件描述制造半导体器件的方法和装置
公开(公告)号：US20090150843A1
公开(公告)日：2009-06-11
申请号：US11951558
申请日：2007-12-06
申请人： Arvind Raman , Ravi Gupta
发明人： Arvind Raman , Ravi Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/14
摘要： A processor-implemented method for making a semiconductor device having a test logic block and a functional logic block is provided. The method includes retrieving hardware description for at least one test logic block and mapping the hardware description for the at least one test logic block to logic gates to generate at least one synthesized test logic block. The method further comprises retrieving hardware description for at least one functional logic block and mapping the hardware description for the at least one functional logic block to logic gates to generate at least one synthesized functional logic block. The method further includes merging the at least one synthesized test logic block with the at least one synthesized functional logic block when the at least one functional logic block meets at least one criterion for selection as a candidate for merger with the at least one test logic block.
摘要翻译：提供了一种用于制造具有测试逻辑块和功能逻辑块的半导体器件的处理器实现的方法。该方法包括检索至少一个测试逻辑块的硬件描述，并将至少一个测试逻辑块的硬件描述映射到逻辑门以生成至少一个合成测试逻辑块。该方法还包括检索至少一个功能逻辑块的硬件描述，并将至少一个功能逻辑块的硬件描述映射到逻辑门以生成至少一个合成功能逻辑块。该方法还包括当至少一个功能逻辑块满足至少一个用于选择的标准作为用于与至少一个测试逻辑块合并的候选者时，将至少一个合成测试逻辑块与至少一个合成功能逻辑块合并。

5. 发明申请

US20050265454A1 Fast motion-estimation scheme 有权
标题翻译：快速运动估计方案
公开(公告)号：US20050265454A1
公开(公告)日：2005-12-01
申请号：US11126533
申请日：2005-05-11
申请人： Murali Muthukrishnan , Arvind Raman , Bhavani Rao , Manish Singhal , Sankaranarayanan Parameswaran , Sriram Sethuraman , Dileep Tamia
发明人： Murali Muthukrishnan , Arvind Raman , Bhavani Rao , Manish Singhal , Sankaranarayanan Parameswaran , Sriram Sethuraman , Dileep Tamia
IPC分类号： H04N5/14 , H04N7/12 , H04N7/26
CPC分类号： H04N19/53 , H04N5/145
摘要： A motion estimation algorithm finds the best match for a given block or macroblock so that the resulting error signal has very low energy level which is computed, for e.g., by the SAD method. The motion estimation algorithm also provides for an optional sub-pixel level estimation and an inter4v search, and allows for restricting the number of searches for a Frame-frame ME (motion estimation) using Top-Top and Bottom-Bottom field MEs. The algorithm provides for a selective early exit and enables selecting a suitable search area with N candidate points (4 to 8) for starting the search. The search is conducted progressively till a minimum error signal (low energy level signal) is reached. The candidate points for search may be in a diamond shaped configuration, and there may be a plurality of successive diamond configurations, the number of which is configurable. The invention has application in MPEG-4 and H.264 standards.
摘要翻译：运动估计算法找到给定块或宏块的最佳匹配，使得所得到的误差信号具有非常低的能级，例如通过SAD方法计算。运动估计算法还提供了可选的子像素级估计和inter4v搜索，并且允许使用Top-Top和Bottom-Bottom-field ME限制对帧帧ME（运动估计）的搜索次数。该算法提供选择性提前退出，并且使得能够选择具有用于开始搜索的N个候选点（4至8）的合适的搜索区域。搜索逐渐进行，直到达到最小误差信号（低能级信号）。用于搜索的候选点可以是菱形配置，并且可以存在多个连续的菱形配置，其数量是可配置的。本发明适用于MPEG-4和H.264标准。

6. 发明授权

US06713942B2 Piezoelectric device with feedback sensor 有权
标题翻译：带反馈传感器的压电器件
公开(公告)号：US06713942B2
公开(公告)日：2004-03-30
申请号：US09863832
申请日：2001-05-23
申请人： Arvind Raman , Suresh V. Garimella
发明人： Arvind Raman , Suresh V. Garimella
IPC分类号： H01L4109
CPC分类号： F04D33/00 , H01L41/08
摘要： A piezoelectric device, such as a piezoelectric fan or microjet generator, for moving a fluid comprising a fluid-moving member having a first piezoelectric (PZT) actuator element coupled thereto to drive or actuate the movable member and a second piezoelectric (PZT) sensing element coupled thereto to provide feedback information related to fluid parameter. The second PZT element also can be used to drive the movable member in conjunction with the first PZT element. The feedback information can be used by a controller to control operation of the piezoelectric device.
摘要翻译：一种压电装置，例如压电风扇或微型喷气发生器，用于移动包括流体移动构件的流体，该流体移动构件具有联接到其上的第一压电（PZT）致动器元件以驱动或致动可动构件，以及第二压电（PZT）感测元件耦合以提供与流体参数相关的反馈信息。第二PZT元件也可用于与第一PZT元件一起驱动可移动元件。控制器可以使用反馈信息来控制压电装置的操作。

7. 发明公开

US20230315483A1 PROCESSOR CORE SUBSYSTEM WITH OPEN-STANDARD NETWORK-ON-CHIP PORTS 审中-公开
公开(公告)号：US20230315483A1
公开(公告)日：2023-10-05
申请号：US17712106
申请日：2022-04-02
申请人： Shih Jun Chong , Ignacio Celis , Krishnakumar Ganapathy , Sang Kim , Chuan Yin Loo , Sanjoy K. Mondal , Mukesh Patel , Arvind Raman , Joseph Rowlands , Shankar Narayanan Venkat Ramani
发明人： Shih Jun Chong , Ignacio Celis , Krishnakumar Ganapathy , Sang Kim , Chuan Yin Loo , Sanjoy K. Mondal , Mukesh Patel , Arvind Raman , Joseph Rowlands , Shankar Narayanan Venkat Ramani
IPC分类号： G06F9/4401 , G06F9/48 , G06F9/38 , G06F9/30
CPC分类号： G06F9/4405 , G06F9/4887 , G06F9/3877 , G06F9/30123
摘要： Embodiments of apparatuses, methods, and machine-readable mediums for a subsystem with open-standard network-on-chip ports are disclosed. In an embodiment, a machine-readable medium includes a design of an apparatus to be manufactured, the apparatus to include one or more cores, and a network-on-chip having at least one port of a first type and at least one port of a second type. The first type is to communicate with the one or more cores according to a proprietary protocol. The second type is to communicate with an intellectual property block according to an open-standard protocol.

8. 发明申请

US20140359328A1 METHOD AND SYSTEM FOR RUN-TIME REALLOCATION OF LEAKAGE CURRENT AND DYNAMIC POWER SUPPLY CURRENT 有权
标题翻译：泄漏电流和动态电源电流的运行时间重新排列的方法和系统
公开(公告)号：US20140359328A1
公开(公告)日：2014-12-04
申请号：US13903744
申请日：2013-05-28
申请人： James S. Burns , Ashish V. Choubal , Arvind Raman , Johan G. Van De Groenendaal
发明人： James S. Burns , Ashish V. Choubal , Arvind Raman , Johan G. Van De Groenendaal
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/206 , G06F1/26 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/329
摘要： A method and system for dynamic or run-time reallocation of leakage current and dynamic power supply current of a processor. In one embodiment of the invention, the processor uses the variation in the leakage current of the processor to reduce the maximum current dissipation or power supply current of the processor (ICCmax). By reducing the maximum current dissipation, the system cost can be reduced as a less expensive power delivery system is required in one embodiment of the invention.
摘要翻译：一种用于处理器的漏电流和动态电源电流的动态或运行时重新分配的方法和系统。在本发明的一个实施例中，处理器使用处理器的漏电流的变化来减小处理器的最大电流消耗或电源电流（ICCmax）。通过减少最大电流消耗，可以减少系统成本，因为在本发明的一个实施例中需要较便宜的电力输送系统。

9. 发明申请

US20110041224A1 ATOMIC FORCE MICROSCOPE INCLUDING ACCELEROMETER 审中-公开
标题翻译：原子力显微镜，包括加速度计
公开(公告)号：US20110041224A1
公开(公告)日：2011-02-17
申请号：US12852095
申请日：2010-08-06
申请人： Arvind Raman , Ronald G. Reifenberger , John T. Melcher
发明人： Arvind Raman , Ronald G. Reifenberger , John T. Melcher
IPC分类号： G01Q60/24
CPC分类号： G01Q60/34 , G01Q60/38
摘要： A microcantilever used in Atomic Force Microscopy (AFM) includes an elongated cantilevered body with a probe tip placed preferably near its free end and preferably along the cantilever's axis. Some embodiments of the present invention integrate into the microcantilever body an embedded or etched paddle that rotates rigidly about an axis parallel to that of the cantilever with hinges that connect the paddle to the cantilever body. In one embodiment the resonance frequency of this paddle resonator is higher than the fundamental resonance of the microcantilever so that the paddle rotation is proportional to the vertical microcantilever acceleration at the hinge location. The motion of the paddle can be detected using radiation irradiating the paddle; the reflected beam is centered onto a four quadrant photodiode as commonly found in AFM. The paddle's vertical motion is detected in the usual way by monitoring the vertical channel in the photodiode while its rotation is monitored from the lateral channel in the photodiode. By monitoring the vertical tip acceleration signal from the paddle rotation, it is possible to resolve the history of tip-sample force during oscillation cycles. A calibration method to convert the measured paddle rotation into vertical probe tip acceleration and instantaneous tip-sample force is also disclosed.
摘要翻译：用于原子力显微镜（AFM）的微悬臂梁包括细长的悬臂体，探针尖端优选地位于其自由端附近，优选沿着悬臂的轴线。本发明的一些实施例将嵌入或蚀刻的桨叶整体结合到微悬臂体中，所述桨叶围绕平行于悬臂的轴旋转，所述铰链将桨连接到悬臂体。在一个实施例中，该桨式谐振器的谐振频率高于微悬臂梁的基本共振，使得桨叶旋转与铰链位置处的垂直微悬臂梁加速度成比例。可以使用辐射桨的辐射来检测桨的运动; 反射光束集中在AFM中通常发现的四象限光电二极管上。通过监测光电二极管中的垂直通道，同时从光电二极管中的横向通道监测其转动，通常以通常的方式检测桨的垂直运动。通过监测来自桨叶旋转的垂直尖端加速度信号，可以在振荡周期期间解析尖端采样力的历史。还公开了一种用于将测量的桨叶旋转转换成垂直探针尖端加速度和瞬时尖峰样本力的校准方法。

10. 发明申请

US20160282930A1 TECHNOLOGIES FOR MANAGING POWER DURING AN ACTIVATION CYCLE 有权
标题翻译：在激活循环中管理功率的技术
公开(公告)号：US20160282930A1
公开(公告)日：2016-09-29
申请号：US14671750
申请日：2015-03-27
申请人： Aswin Ramachandran , Arvind Raman
发明人： Aswin Ramachandran , Arvind Raman
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/3228 , G06F1/324 , G06F1/3296 , G06F9/4418 , G06F11/0724 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.
摘要翻译：在处理器核心或其他计算域的激活周期期间管理电源的技术包括在休眠处理器核心或其他休眠计算域的激活周期期间确定主动处理器内核或其他计算域的新操作限制，以减少功率的可能性在激活休眠处理器核心或其他计算域期间激增。监视活动处理器核心或其他计算域，直到其工作点处于或低于新的操作限制。此后，激活休眠处理器内核或其他休眠计算域。

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