专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100310030A1 PHASE LOCKED LOOP DEVICE AND METHOD THEREOF 有权
标题翻译：相位锁定环路装置及其方法
公开(公告)号：US20100310030A1
公开(公告)日：2010-12-09
申请号：US12480344
申请日：2009-06-08
申请人： Gayathri A. Bhagavatheeswaran , Joseph P. Gergen , Arvind Raman , Hector Sanchez
发明人： Gayathri A. Bhagavatheeswaran , Joseph P. Gergen , Arvind Raman , Hector Sanchez
IPC分类号： H03D3/24
CPC分类号： H03D13/00 , G11C7/222 , G11C29/1201 , H03L7/0805
摘要： A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, in indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.
摘要翻译：锁相环装置包括相位检测器，该相位检测器测量参考时钟信号和提供给器件模块的输出时钟信号之间的相位差。相位检测器提供具有指示相位差的宽度的脉冲。如果相位差超过多个阈值中的一个，则可以确定in指示符。基于指示器，控制模块可以采取补救措施，例如向设备模块提供不同的时钟信号或在处理器设备触发中断。

2. 发明授权

US4785411A Cascade filter structure with time overlapped partial addition operations and programmable tap length 失效
标题翻译：级联滤波器结构，具有时间重叠部分加法运算和可编程抽头长度
公开(公告)号：US4785411A
公开(公告)日：1988-11-15
申请号：US901850
申请日：1986-08-29
申请人： Charles D. Thompson , Joseph P. Gergen , Bradley Martin , Garth D. Hillman
发明人： Charles D. Thompson , Joseph P. Gergen , Bradley Martin , Garth D. Hillman
IPC分类号： H03H17/02 , G06F7/38
CPC分类号： H03H17/0211
摘要： A filter structure uses multiple discrete filter circuits which are cascaded to provide a multiple tap filter of programmable tap length. In one form, an FIR filter may be implemented wherein each circuit generates partial sum operands which must be added to provide a filter output. The cascaded circuits perform partial addition operations near simultaneously by using a serial addition which is synchronized with a start bit. The number of taps in the filter structure implemented by the cascaded discrete filter circuits is variable and may be programmed with a programmable storage register in each discrete circuit which stores operand data fixing the tap length of each discrete circuit. The multiple filter circuits provide a single filter structure with a large tap length and high sampling rate.
摘要翻译：滤波器结构使用多个分离滤波器电路，它们被级联以提供可编程分接头长度的多抽头滤波器。在一种形式中，可以实现FIR滤波器，其中每个电路产生必须被相加以提供滤波器输出的部分和操作数。级联电路通过使用与起始位同步的串行加法来同时执行部分加法运算。由级联离散滤波器电路实现的滤波器结构中的抽头数量是可变的，并且可以在每个分立电路中用可编程存储寄存器来编程，其存储固定每个分立电路的抽头长度的操作数。多个滤波器电路提供具有大抽头长度和高采样率的单个滤波器结构。

3. 发明申请

US20150347185A1 EXPLICIT BARRIER SCHEDULING MECHANISM FOR PIPELINING OF STREAM PROCESSING ALGORITHMS 有权
标题翻译：用于流水线加工算法的显式障碍物调度机制
公开(公告)号：US20150347185A1
公开(公告)日：2015-12-03
申请号：US14288541
申请日：2014-05-28
申请人： James C. Holt , Joseph P. Gergen , David B. Kramer , William C. Moyer
发明人： James C. Holt , Joseph P. Gergen , David B. Kramer , William C. Moyer
IPC分类号： G06F9/48 , G06F9/38
CPC分类号： H04L49/00
摘要： A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. In response to determining a first storage location stores a first barrier indicator, enabling the first task portion to process the first packet and storing a second barrier indicator at the first location. Determining the first task portion is to process a second next-in-order packet. In response to determining the first location stores the second barrier indicator, preventing the first task portion from processing the second packet. In response to a first barrier clear indicator, storing the first barrier indicator at the first location, and in response, enabling the first task portion to process the second packet.
摘要翻译：用于数据流的流水线数据流处理的方法包括确定要在数据流的每个分组上执行的任务，所述任务具有包括第一任务部分的多个任务部分。确定第一任务部分是处理第一分组。响应于确定第一存储位置存储第一屏障指示符，使第一任务部分能够处理第一分组并在第一位置存储第二屏障指示符。确定第一任务部分是处理第二次序的分组。响应于确定第一位置存储第二屏障指示符，防止第一任务部分处理第二分组。响应于第一屏障清除指示符，将第一屏障指示器存储在第一位置处，并且作为响应，使得第一任务部分能够处理第二分组。

4. 发明授权

US06842895B2 Single instruction for multiple loops 有权
标题翻译：多个循环的单指令
公开(公告)号：US06842895B2
公开(公告)日：2005-01-11
申请号：US09746978
申请日：2000-12-21
申请人： Pascal L. Renard , Joseph P. Gergen
发明人： Pascal L. Renard , Joseph P. Gergen
IPC分类号： G06F9/32 , G06F9/45
CPC分类号： G06F9/325
摘要： Embodiments of the present invention relate generally to the manner in which processors execute multiple loop instructions. That is, embodiments of the invention relate to the organization of multiple loop constructs, such as, for example, nested loops, to achieve improved performance during loop execution. One embodiment contemplates a single instruction that provides for execution of other instructions of a set of instructions in accordance with multiple looping constructs. Another embodiment contemplates a single-loop instruction suitable for terminating on multiple termination conditions.
摘要翻译：本发明的实施例一般涉及处理器执行多个循环指令的方式。也就是说，本发明的实施例涉及多个循环结构的组织，例如嵌套循环，以在循环执行期间实现改进的性能。一个实施例考虑了根据多个循环结构提供执行一组指令的其他指令的单个指令。另一个实施例考虑适用于在多个终止条件下终止的单循环指令。

5. 发明授权

US08509370B2 Phase locked loop device and method thereof 有权
标题翻译：锁相环装置及其方法
公开(公告)号：US08509370B2
公开(公告)日：2013-08-13
申请号：US12480344
申请日：2009-06-08
申请人： Gayathri A. Bhagavatheeswaran , Joseph P. Gergen , Arvind Raman , Hector Sanchez
发明人： Gayathri A. Bhagavatheeswaran , Joseph P. Gergen , Arvind Raman , Hector Sanchez
IPC分类号： H03D3/24
CPC分类号： H03D13/00 , G11C7/222 , G11C29/1201 , H03L7/0805
摘要： A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, an indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.
摘要翻译：锁相环装置包括相位检测器，该相位检测器测量参考时钟信号和提供给器件模块的输出时钟信号之间的相位差。相位检测器提供具有指示相位差的宽度的脉冲。如果相位差超过多个阈值中的一个，则可以断言指示符。基于指示器，控制模块可以采取补救措施，例如向设备模块提供不同的时钟信号或在处理器设备触发中断。

6. 发明申请

US20100318752A1 Event Triggered Memory Mapped Access 有权
标题翻译：事件触发内存映射访问
公开(公告)号：US20100318752A1
公开(公告)日：2010-12-16
申请号：US12485190
申请日：2009-06-16
申请人： William D. Schwarz , Joseph P. Gergen , Jason T. Nearing , Zheng Xu
发明人： William D. Schwarz , Joseph P. Gergen , Jason T. Nearing , Zheng Xu
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F11/3636
摘要： In one or more embodiments, a data processing system can include at least one core capable of executing instructions of an instruction set architecture and a triggered memory map access (tMMA) system coupled to the at least one core. The tMMA system can receive one or more events and, in response, perform one or more actions. For example, the actions can include transactions which can include a write to a an address of the memory map, a read from an address of the memory map, a read followed by write to two respective addresses of the memory map, and/or a fetch transaction. A result of a transaction (e.g., data read, data written, error, etc.) can be used in generating a trace message. For example, the tMMA system can generate a trace message that includes the result of the transaction and send the trace message to a trace message bus.
摘要翻译：在一个或多个实施例中，数据处理系统可以包括能够执行指令集架构的指令的至少一个核心以及耦合到所述至少一个核心的触发的存储器映射访问（tMMA）系统。 tMMA系统可以接收一个或多个事件，并作为响应执行一个或多个动作。例如，动作可以包括可以包括对存储器映射的地址的写入，从存储器映射的地址的读取，随后写入存储器映射的两个相应地址的读取的事务，和/或提取事务。事务的结果（例如，数据读取，数据写入，错误等）可用于生成跟踪消息。例如，tMMA系统可以生成包含事务结果的跟踪消息，并将跟踪消息发送到跟踪消息总线。

7. 发明授权

US07107489B2 Method and apparatus for debugging a data processing system 有权
标题翻译：用于调试数据处理系统的方法和装置
公开(公告)号：US07107489B2
公开(公告)日：2006-09-12
申请号：US10202946
申请日：2002-07-25
申请人： Joseph P. Gergen , Tan Nhat Dao , Jerome Hannah
发明人： Joseph P. Gergen , Tan Nhat Dao , Jerome Hannah
IPC分类号： G06F11/00
CPC分类号： G06F11/3648
摘要： A data processing system (10) includes a CPU (12) and debug circuitry (16). CPU (12) can execute instructions which provide direct input to one or more of trigger circuitry (32), multi-function debug counters (34), combining logic (36), and action select and control logic (38). Breakpoints can be cascaded, and separate breakpoint sequences can be triggered from a same trigger. A selected trigger (117) can produce a resulting action or trigger (119) but only if it occurs in a predetermined order compared to one or more other triggers (117). Multi-function debug counters (34) can perform a wide variety of programmable functions, can be started and stopped using the same or separate triggers, and can be optionally concatenated with each other.
摘要翻译：数据处理系统（10）包括CPU（12）和调试电路（16）。 CPU（12）可以执行向触发电路（32），多功能调试计数器（34），组合逻辑（36）和动作选择和控制逻辑（38）中的一个或多个提供直接输入的指令。断点可以级联，并且可以从相同的触发器触发单独的断点序列。所选择的触发器（117）可以产生所产生的动作或触发器（119），但是仅当其与一个或多个其他触发器（117）相比以预定顺序发生时。多功能调试计数器（34）可以执行各种可编程功能，可以使用相同或不同的触发器启动和停止，并且可以可选地相互连接。

8. 发明授权

US5001665A Addressing technique for providing read, modify and write operations in a single data processing cycle with serpentine configured RAMs 失效
标题翻译：用于在单个数据处理周期中提供读取，修改和写入操作的寻址技术，具有蛇形配置的RAM
公开(公告)号：US5001665A
公开(公告)日：1991-03-19
申请号：US878926
申请日：1986-06-26
申请人： Joseph P. Gergen , Charles D. Thompson
发明人： Joseph P. Gergen , Charles D. Thompson
IPC分类号： G06F9/34 , G06F12/06
CPC分类号： G06F12/0607
摘要： A technique for accomplishing a read, modify and write operation of a memory in a processor in a single cycle of the processor, where a cycle is understood as the time between successive loads of operands to the processor. A memory having two distinct portions of operands is provided wherein the single cycle operations are accomplished by virtually addressing the operands in a serpentine or snake-like configuration. A decoder is provided for efficiently controlling the concurrent reading and writing of operands and controlling the addressing of the memory.
摘要翻译：一种用于在处理器的单个周期中完成处理器中的存储器的读取，修改和写入操作的技术，其中周期被理解为处理器的操作数的连续加载之间的时间。提供了具有操作数的两个不同部分的存储器，其中通过以蛇形或蛇形配置虚拟地寻址操作数来实现单周期操作。提供了一种解码器，用于有效地控制并行读取和写入操作数并控制存储器的寻址。

9. 发明授权

US06751759B1 Method and apparatus for pipeline hazard detection 失效
标题翻译：管道危害检测方法与装置
公开(公告)号：US06751759B1
公开(公告)日：2004-06-15
申请号：US09706089
申请日：2000-11-03
申请人： Xiao Sun , Chi Duong , Joseph P. Gergen
发明人： Xiao Sun , Chi Duong , Joseph P. Gergen
IPC分类号： G06F1100
CPC分类号： G06F11/0721 , G06F11/0754 , G06F11/3409 , G06F11/3419
摘要： A method and apparatus for identifying and detecting hazards is presented. An executable specification for the architecture is compiled that includes macroarchitecture and microarchitecture information corresponding to each of the instructions supported by the architecture. A table (20) is constructed from the executable specification that specifies the particular resource utilization parameters associated with each of the instruction types included in the instruction set supported. From this table a resource utilization parameter list (30) is compiled that indicates the relative times at which resources are needed by each instruction and when these resources are released by the instruction. Comparisons between different entries in the resource utilization parameter list corresponding to the same resource are performed such that potential hazards are detected. A hazard list (200) is then compiled that includes all of the hazards detected through the comparison operations utilizing the resource utilization parameter list (30).
摘要翻译：提出了一种用于识别和检测危害的方法和装置。该架构的可执行规范被编译，其中包括与架构支持的每个指令相对应的宏架构和微体系结构信息。从可执行规范构建表（20），其指定与支持的指令集中包括的每个指令类型相关联的特定资源利用参数。从该表中，编译资源利用参数列表（30），其指示每个指令需要资源的相对时间，以及当指令释放这些资源时。执行对应于相同资源的资源利用率参数列表中的不同条目之间的比较，以便检测到潜在危险。然后编译危险列表（200），其包括利用资源利用参数列表（30）通过比较操作检测到的所有危险。

10. 发明授权

US5442576A Multibit shifting apparatus, data processor using same, and method therefor 失效
标题翻译：多位移位装置，使用其的数据处理装置及其方法
公开(公告)号：US5442576A
公开(公告)日：1995-08-15
申请号：US249505
申请日：1994-05-26
申请人： Joseph P. Gergen , Kin K. Chau-Lee
发明人： Joseph P. Gergen , Kin K. Chau-Lee
IPC分类号： G06F7/00 , G06F5/01 , G06F7/53 , G06F7/76 , G06F7/52
CPC分类号： G06F5/015
摘要： A multibit shifting apparatus (50) of a data processor (40) includes a multiplier (55) such as a modified Booth's recoded multiplier for use in normal multiplication operations. The multibit shifting apparatus (50) also uses the multiplier (55) to perform programmable left and right shifts in order to save circuit area. During a shift operation, a remapping circuit (54) receives a shift count, and remaps the shift count according to a shift direction to provide a remapped signal. The multiplier (55) receives both a shift operand and the remapped signal at inputs thereof. The multiplier (55) provides a first shift result at its output. In one embodiment, an output shifter (57) shifts the first shift result by a fixed amount selectively according to the shift direction to provide a second shift result. The second shift result includes outputs of both left and right shifts in common bit positions.
摘要翻译：数据处理器（40）的多位移位装置（50）包括乘法器（55），例如用于正常乘法运算的经修改的布斯重编码乘法器。多位移位装置（50）还使用乘法器（55）来执行可编程的左移和右移，以节省电路面积。在换档操作期间，重映射电路（54）接收移位计数，并根据移位方向对移位计数重新进行重新映射以提供重新映射的信号。乘法器（55）在其输入处接收移位操作数和重映射信号。乘法器（55）在其输出端提供第一个移位结果。在一个实施例中，输出移位器（57）根据移位方向选择性地将第一移位结果移位固定量以提供第二移位结果。第二移位结果包括在公共位位置的左右移位的输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式