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    • 2. 发明申请
    • JAVA HARDWARE ACCELERATOR USING MICROCODE ENGINE
    • JAVA硬件加速器使用微型发动机
    • US20070118724A1
    • 2007-05-24
    • US11538362
    • 2006-10-03
    • Mukesh Patel
    • Mukesh Patel
    • G06F9/30
    • G06F9/30174G06F9/3879
    • A hardware Java accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt. A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.
    • 硬件Java加速器由解码级和微码级组成。 分解为解码和微码级允许解码级实现指令级并行性,而微代码级允许将单个Java字节码转换为多个本机指令。 提供重发缓冲器,其存储转换的指令,并且当系统从中断返回时重新发行它们。 以这种方式,硬件加速器不必在中断时被刷新。 还使用本机PC显示器。 当本机PC在特定范围内时,硬件加速器能够将Java字节码转换为本地指令。 当本地PC超出该范围时,硬件加速器被禁用,并且CPU对从存储器获得的本地指令进行操作。
    • 4. 发明授权
    • Methods, apparatuses and computer program products for determining speed of movement of a device and device pose classification
    • 用于确定设备和设备姿态分类的移动速度的方法,设备和计算机程序产品
    • US09069003B2
    • 2015-06-30
    • US13458580
    • 2012-04-27
    • Jonathan LedlieJun-geun ParkAmi Mukesh PatelDorothy CurtisSeth Teller
    • Jonathan LedlieJun-geun ParkAmi Mukesh PatelDorothy CurtisSeth Teller
    • G06F19/00G01P3/60
    • G01P3/60
    • An apparatus for determining a speed of cyclic motion of a device or user and one or more poses of a device may include a processor and memory storing executable computer code causing the apparatus to at least perform operations including receiving one or more determined acceleration values during one or more time periods in response to detected cyclic motion of a user moving with an apparatus. The computer program code may further cause the apparatus to transform the acceleration values to one or more corresponding frequency components associated with the acceleration values. The computer program code may further cause the apparatus to determine a speed of the cyclic motion of the user based in part on comparing a spectrum of the frequency components to one or more spectrums of distribution associated with respective one or more speeds of training data. Corresponding methods and computer program products are also provided.
    • 用于确定设备或用户的循环运动的速度以及设备的一个或多个姿势的装置可以包括处理器和存储器,其存储可执行的计算机代码,使得该设备至少执行操作,包括在一个 响应于用设备移动的用户的检测到的循环运动,或更多的时间段。 计算机程序代码还可以使设备将加速度值转换成与加速度值相关联的一个或多个对应的频率分量。 计算机程序代码可以进一步使得设备基于将频率分量的频谱与与相应的一个或多个训练数据的速度相关联的一个或多个分布频谱进行比较来确定用户的循环运动的速度。 还提供了相应的方法和计算机程序产品。
    • 9. 发明授权
    • Method and system for coupling a stack based processor to register based
functional unit
    • 用于将基于堆栈的处理器耦合到基于寄存器的功能单元的方法和系统
    • US6088786A
    • 2000-07-11
    • US884255
    • 1997-06-27
    • Gary FeierbachMukesh Patel
    • Gary FeierbachMukesh Patel
    • G06F9/30G06F9/38G06F15/78G06F15/00
    • G06F9/30134G06F15/7832G06F9/3879
    • A microprocessor capable of performing multimedia and non-multimedia operations provided a plurality of stack based instructions is provided. The microprocessor includes a stack processor coupled to a stack capable of storing values, a register processor coupled to a register file capable of storing values, and a copy-unit having a first port coupled to the stack and a second port coupled to the register file being configured to copy data between the register file and the stack. The microprocessor also includes logic coupled to receive the plurality of stack based instructions from memory, cache, or other storage devices coupled to the microprocessor. The logic is configured to determine which of the plurality of stack based instructions are regular stack instructions and which of the plurality of stack based instructions are extended stack instructions. A stack decoder having a first port coupled to the logic and a second port coupled to the stack processor is configured to decode the regular stack instructions and provide control signals to the stack processor. A copy-unit decoder having a first port coupled to the logic and a second port coupled to the copy-unit is configured to decode extended stack instructions and provide control signals to the copy-unit. Further, a register processor decoder having a first port coupled to the logic and a second port coupled to the register processor is configured to decode extended stack instructions and provide the decoded extended stack instructions to the register processor.
    • 提供了能够执行多媒体和非多媒体操作的微处理器,提供了多个基于堆栈的指令。 微处理器包括耦合到能够存储值的堆栈的堆栈处理器,耦合到能够存储值的寄存器文件的寄存器处理器,以及具有耦合到堆栈的第一端口的复制单元和耦合到寄存器堆的第二端口 被配置为在寄存器文件和堆栈之间复制数据。 微处理器还包括耦合以从存储器,高速缓存或耦合到微处理器的其它存储设备接收多个基于堆栈的指令的逻辑。 逻辑被配置为确定多个基于堆栈的指令中的哪一个是常规堆栈指令,以及多个基于堆栈的指令中的哪一个是扩展堆栈指令。 具有耦合到逻辑的第一端口和耦合到堆栈处理器的第二端口的堆栈解码器被配置为对常规栈指令进行解码,并向堆栈处理器提供控制信号。 具有耦合到逻辑的第一端口和耦合到复制单元的第二端口的复制单元解码器被配置为解码扩展堆栈指令并向复制单元提供控制信号。 此外,具有耦合到逻辑的第一端口和耦合到寄存器处理器的第二端口的寄存器处理器解码器被配置为解码扩展堆栈指令并将解码的扩展堆栈指令提供给寄存器处理器。