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1. 发明授权

US07330078B1 Apparatus and method for limiting the overshoot and undershoot when turning on the spread spectrum of a reference signal 失效
标题翻译：当开启参考信号的扩展频谱时，限制过冲和下冲的装置和方法
公开(公告)号：US07330078B1
公开(公告)日：2008-02-12
申请号：US11300718
申请日：2005-12-13
申请人： Gabriel Li , Dusan Vecera
发明人： Gabriel Li , Dusan Vecera
IPC分类号： H03L7/06
CPC分类号： H03L7/18
摘要： Disclosed is a circuit, comprising an input spread spectrum enable signal, a crystal oscillator, a first, second and third sampling flip-flop clocked by the crystal oscillator, configured to sample the input spread spectrum enable signal, and a plurality of control output signals derived from or provided directly from the sampling flip-flops. A method of operating the circuit is further described.
摘要翻译：公开了一种电路，包括输入扩频使能信号，晶体振荡器，由晶体振荡器定时的第一，第二和第三采样触发器，被配置为对输入扩频使能信号进行采样，以及多个控制输出信号来自或直接从采样触发器提供。进一步描述操作电路的方法。

2. 发明授权

US07138841B1 Programmable phase shift and duty cycle correction circuit and method 有权
标题翻译：可编程相移和占空比校正电路及方法
公开(公告)号：US07138841B1
公开(公告)日：2006-11-21
申请号：US11014578
申请日：2004-12-16
申请人： Gabriel Li , Chwei-Po Chew , Dusan Vecera
发明人： Gabriel Li , Chwei-Po Chew , Dusan Vecera
IPC分类号： H03K3/017
CPC分类号： H03K5/151 , H03K5/1565 , H03K2005/00058 , H03K2005/00156
摘要： A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and dump sub-circuit for charging and discharging the storage device, respectively, a comparator, and a clock driver circuit. A linearly increasing (or ramped) voltage waveform is generated within the storage device by the charging and discharging actions of the charge and dump sub-circuits; a periodic process which is controlled by opposite phases of the input clock. By programming the DAC control input to change the slicing threshold of the ramped waveform, the circuit and method described herein provides a means for programmable phase shifting and duty cycle correction.
摘要翻译：本文公开了一种相移和占空比校正电路，其包括可编程数模转换器（DAC），存储装置（例如，电容器），用于对存储装置进行充电和放电的充电子电路和转储子电路一个比较器和一个时钟驱动电路。通过充电和转储子电路的充电和放电动作，在存储装置内产生线性增加（或斜坡）的电压波形; 周期性过程由输入时钟的相反相位控制。通过对DAC控制输入进行编程以改变斜坡波形的限幅门限，本文描述的电路和方法提供了可编程相移和占空比校正的方法。

3. 发明授权

US07876133B1 Output buffer circuit 有权
标题翻译：输出缓冲电路
公开(公告)号：US07876133B1
公开(公告)日：2011-01-25
申请号：US11904901
申请日：2007-09-27
申请人： Alan McLaughlin , Gabriel Li
发明人： Alan McLaughlin , Gabriel Li
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/018521
摘要： An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.
摘要翻译：输出驱动器电路可以包括至少第一驱动器晶体管，其具有耦合在第一电源节点和输出节点之间的源极 - 漏极路径。第一可变电流源可以产生具有与电源电压成反比的至少一个分量的电流。第一驱动器开关元件可以与至少第一驱动器晶体管的栅极和第二电源节点之间的第一可变电流源串联耦合。

4. 发明申请

US20110016374A1 SERIAL INTERFACE DEVICES, SYSTEMS AND METHODS 有权
标题翻译：串行接口设备，系统和方法
公开(公告)号：US20110016374A1
公开(公告)日：2011-01-20
申请号：US12838035
申请日：2010-07-16
申请人： Edward L. Grivna , Gabriel Li , Thinh Tran
发明人： Edward L. Grivna , Gabriel Li , Thinh Tran
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F13/4291 , G06F11/1016
摘要： A serial interface device may include a plurality of serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values.
摘要翻译：串行接口设备可以包括多个串行链路连接，其至少在不同的串行链路连接上接收地址值和至少一个错误检测码（EDC），EDC至少从地址值生成。

5. 发明申请

US20100026345A1 CIRCUIT, SYSTEM, AND METHOD FOR MULTIPLEXING SIGNALS WITH REDUCED JITTER 有权
标题翻译：具有减少抖动信号的多路复用信号的电路，系统和方法
公开(公告)号：US20100026345A1
公开(公告)日：2010-02-04
申请号：US12577477
申请日：2009-10-12
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03K19/00 , H03K17/16
CPC分类号： H04J3/047 , H03K17/002 , H03K19/1737
摘要： An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.
摘要翻译：一种具有多个电源域和多个逻辑部件的装置。多个逻辑组件中的每一个驻留在多个电源域中的不同的一个中。所述多个逻辑部件中的每一个被配置为与所述多个电源域中的相应一个中的对应的时钟信号一起操作。

6. 发明授权

US06597707B1 Circuitry, architecture and methods for synchronizing data 有权
标题翻译：用于同步数据的电路，架构和方法
公开(公告)号：US06597707B1
公开(公告)日：2003-07-22
申请号：US09391967
申请日：1999-09-08
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H04L2536
CPC分类号： G06F5/10 , H04L7/005 , H04L7/033 , H04L7/04
摘要： An apparatus comprising a first programmable circuit configured to present (i) a first parallel data signal and (ii) a first control signal in response to one or more serial data signals and a second programmable circuit configured to generate a second parallel data signal in response to (i) the first parallel data signal, (ii) the first control signal and (iii) a second control signal.
摘要翻译：一种装置，包括第一可编程电路，其被配置为响应于一个或多个串行数据信号呈现（i）第一并行数据信号和（ii）第一控制信号，以及第二可编程电路，其被配置为响应于产生第二并行数据信号（i）第一并行数据信号，（ii）第一控制信号和（iii）第二控制信号。

7. 发明授权

US06181717B2 Tunable semiconductor laser system 有权
公开(公告)号：US06181717B2
公开(公告)日：2001-01-30
申请号：US09326010
申请日：1999-06-04
申请人： Peter Kner , Gabriel Li , Philip Worland , Rang-Chen Yu , Wupen Yuen
发明人： Peter Kner , Gabriel Li , Philip Worland , Rang-Chen Yu , Wupen Yuen
IPC分类号： H01S310
CPC分类号： H01S5/06804 , H01L2224/48091 , H01L2924/16195 , H01S5/0078 , H01S5/02248 , H01S5/0687 , H01S5/18366 , H01L2924/00014
摘要： A tunable semiconductor laser system includes a laser with a semiconductor active region positioned between upper and lower confining regions of opposite type semiconductor material. First and second reflective members are positioned at opposing edges of the active and confining regions. A wavelength tuning member and a temperature sensor are coupled to the laser. A control loop is coupled to the temperature sensor and the tuning member. In response to a detected change in temperature the control loop sends an adjustment signal to the tuning member and the tuning member adjusts a voltage or current supplied to the laser to provide a controlled output beam of selected wavelength.

8. 发明授权

US5646967A Multi-phase triangular wave synthesizer for phase-to-frequency converter 失效
标题翻译：用于相变频器的多相三角波合成器
公开(公告)号：US5646967A
公开(公告)日：1997-07-08
申请号：US644035
申请日：1996-05-09
申请人： Wong Hee , Gabriel Li
发明人： Wong Hee , Gabriel Li
IPC分类号： G06F1/02 , G06F7/62 , H03L7/08 , H03L7/089 , H04L7/00
CPC分类号： H03L7/089 , G06F1/022 , G06F7/62 , H03L7/08
摘要： A triangular waveform synthesizer for a phase-to-frequency converter generates a saw tooth and triangular wave using both PDM and a DC modulation scheme. To minimize both delay and logic, while continuing to provide reasonable resolution, a 4-bit PDM and associated logic generates the PDM output waveform with polarity information and two switching waveforms that encode the DC level information to provide a resultant sum. The resulting waveform, after filtering, is the triangular waveform. Since the switching and adding of the DC levels occurs in real time, the actual delay for the resultant triangular wave is only that of the 4-bit PDM.
摘要翻译：用于相变频率转换器的三角波形合成器使用PDM和DC调制方案来产生锯齿和三角波。为了最小化延迟和逻辑，在继续提供合理分辨率的同时，4位PDM和相关逻辑产生具有极性信息的PDM输出波形和两个编码直流电平信息的开关波形，以提供最终的和。滤波后的结果波形是三角波形。由于直流电平的切换和加法实时发生，所以产生的三角波的实际延迟只是4位PDM的延迟。

9. 发明授权

US08856434B2 Memory system and method 有权
标题翻译：内存系统和方法
公开(公告)号：US08856434B2
公开(公告)日：2014-10-07
申请号：US12819794
申请日：2010-06-21
申请人： Jun Li , Gabriel Li
发明人： Jun Li , Gabriel Li
IPC分类号： G06F12/00 , G06F13/16 , G06F13/28
CPC分类号： G06F13/28 , G06F13/1684
摘要： In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller.
摘要翻译：在一个实施例中，一种装置包括存储器控制器，其被配置为控制通过菊花链式总线连接的多个菊花链连接的存储器组件。菊花链式总线包括从存储器控制器的发送接口到初始存储器组件的接收接口的直接连接以及从初始存储器组件的发送接口到下一个存储器组件的接收接口的菊花链连接。总线从最后存储器组件的发送接口直接延伸到存储器控制器的接收接口。

10. 发明授权

US07899145B2 Circuit, system, and method for multiplexing signals with reduced jitter 有权
标题翻译：具有减少抖动的信号复用的电路，系统和方法
公开(公告)号：US07899145B2
公开(公告)日：2011-03-01
申请号：US12577477
申请日：2009-10-12
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03D3/24
CPC分类号： H04J3/047 , H03K17/002 , H03K19/1737
摘要： An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.
摘要翻译：一种具有多个电源域和多个逻辑部件的装置。多个逻辑组件中的每一个驻留在多个电源域中的不同的一个中。所述多个逻辑部件中的每一个被配置为与所述多个电源域中的相应一个中的对应的时钟信号一起操作。

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