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1. 发明授权

US08464145B2 Serial interface devices, systems and methods 有权
标题翻译：串行接口设备，系统和方法
公开(公告)号：US08464145B2
公开(公告)日：2013-06-11
申请号：US12838035
申请日：2010-07-16
申请人： Edward L. Grivna , Gabriel Li , Thinh Tran
发明人： Edward L. Grivna , Gabriel Li , Thinh Tran
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F13/4291 , G06F11/1016
摘要： A serial interface device includes multiple serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values, the serial link connections for the address values and EDC operated separately from one another; and multiple output serial links, at least a first one of the output serial links outputting data values read from memory locations corresponding to the address values, and at least a second one of the output serial links different from and operated separately from the first one outputting EDC values generated for the data values read from the memory locations.
摘要翻译：串行接口设备包括多个串行链路连接，其至少在不同的串行链路连接上接收地址值和至少一个错误检测码（EDC），从至少地址值生成的EDC，地址值的串行链路连接以及 EDC彼此分开操作; 和多个输出串行链路，输出串行链路中的至少第一个输出从对应于地址值的存储器位置读取的数据值，以及至少第二个输出串行链路，与第一个输出串行链路不同，并且与第一个串行链路分开运行为从内存位置读取的数据值生成的EDC值。

2. 发明授权

US08218598B1 Method to program the starting phase of the spread spectrum 有权
标题翻译：编程扩频开始阶段的方法
公开(公告)号：US08218598B1
公开(公告)日：2012-07-10
申请号：US12054328
申请日：2008-03-24
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H04B1/00
CPC分类号： H04B15/04
摘要： Disclosed is a circuit and method to program the starting phase of the spread spectrum of a clock output. The circuit includes a plurality of phase locked loop (PLL) circuits for generating a plurality of spread spectrum waveforms. The circuit also includes a spread control circuit for controlling each of the plurality of PLL circuits in accordance with a plurality of respective spread profiles. The spread profiles are configured to vary a starting phase of each spread spectrum waveform such that a total energy of each spread spectrum waveform is out of phase with other spread spectrum waveforms.
摘要翻译：公开了一种用于对时钟输出的扩展频谱的起始阶段进行编程的电路和方法。该电路包括用于产生多个扩展频谱波形的多个锁相环（PLL）电路。电路还包括扩展控制电路，用于根据多个相应的扩展分布来控制多个PLL电路中的每一个。扩展分布被配置为改变每个扩频波形的起始相位，使得每个扩展频谱波形的总能量与其他扩展频谱波形异相。

3. 发明授权

US08095747B2 Memory system and method 有权
标题翻译：内存系统和方法
公开(公告)号：US08095747B2
公开(公告)日：2012-01-10
申请号：US12239532
申请日：2008-09-26
申请人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
发明人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
IPC分类号： G06F12/00
CPC分类号： G06F13/28
摘要： In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.
摘要翻译：在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控制器。配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

4. 发明申请

US20110252162A1 MEMORY SYSTEM AND METHOD 有权
标题翻译：记忆系统和方法
公开(公告)号：US20110252162A1
公开(公告)日：2011-10-13
申请号：US12819794
申请日：2010-06-21
申请人： Jun Li , Gabriel Li
发明人： Jun Li , Gabriel Li
IPC分类号： G06F13/42 , G06F13/14
CPC分类号： G06F13/28 , G06F13/1684
摘要： In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller.
摘要翻译：在一个实施例中，一种装置包括存储器控制器，其被配置为控制通过菊花链式总线连接的多个菊花链连接的存储器组件。菊花链式总线包括从存储器控制器的发送接口到初始存储器组件的接收接口的直接连接以及从初始存储器组件的发送接口到下一个存储器组件的接收接口的菊花链连接。总线从最后存储器组件的发送接口直接延伸到存储器控制器的接收接口。

5. 发明申请

US20100082861A1 MEMORY SYSTEM AND METHOD 有权
标题翻译：记忆系统和方法
公开(公告)号：US20100082861A1
公开(公告)日：2010-04-01
申请号：US12239532
申请日：2008-09-26
申请人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
发明人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
IPC分类号： G06F13/42 , G06F13/40 , G06F13/28
CPC分类号： G06F13/28
摘要： In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.
摘要翻译：在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控制器。配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

6. 发明授权

US07219252B1 Apparatus and method for dynamic overclocking 有权
标题翻译：动态超频的设备和方法
公开(公告)号：US07219252B1
公开(公告)日：2007-05-15
申请号：US10888470
申请日：2004-07-09
申请人： Gabriel Li , Chwei-Po Chew , Johnson Tsai
发明人： Gabriel Li , Chwei-Po Chew , Johnson Tsai
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： According to embodiments of the invention, temperature, current, or other physical quantities associated with an integrated circuit, which can also include a processor, may be converted to a digital signal, and that digital signal used to choose a corresponding frequency offset that is added to any pre-established overclocking frequency. Embodiments of the invention allow a user to specify a dynamic range between which the frequency offset is bounded during overclocking of the integrated circuit. The programmable lower limit specifies the frequency where the integrated circuit begins to overclock. The programmable upper limit specifies the maximum overclocking frequency that is allowed. Setting the lower limit to be equal to the upper limit forces overclocking to occur at only the specified value.
摘要翻译：根据本发明的实施例，与集成电路相关联的温度，电流或其他物理量（其也可以包括处理器）可以被转换为数字信号，并且该数字信号用于选择相应的频率偏移量到任何预先建立的超频频率。本发明的实施例允许用户在集成电路的超频期间指定频率偏移界定的动态范围。可编程下限指定集成电路开始超频的频率。可编程上限指定允许的最大超频频率。将下限设置为等于上限强制超频仅在指定值发生。

7. 发明申请

US20070053475A1 Circuit, System, and Method for Multiplexing Signals with Reduced Jitter 有权
标题翻译：具有减少抖动的多路复用信号的电路，系统和方法
公开(公告)号：US20070053475A1
公开(公告)日：2007-03-08
申请号：US11468195
申请日：2006-08-29
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03D3/24
CPC分类号： H04J3/047 , H03K17/002 , H03K19/1737
摘要： A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply noise injection may be eliminated by: (i) separating the multiplexing function into three separate logic gates and (ii) allowing only one switching input per logic gate. In some cases, jitter may be further reduced by distributing the logic gates across three distinct power domains. In other words, the logic gate inputs may be further isolated by gating each signal in its own power domain. In addition, the multiplexer circuit provides built in delay matching by utilizing three substantially identical logic gates.
摘要翻译：本文提供了一种多路复用器电路，系统和方法，用于通过消除多路复用器电路内的所有串扰和电源噪声注入来复用具有减小的抖动的信号。例如，可以通过以下步骤来消除串扰和电源噪声注入：（i）将多路复用功能分离成三个单独的逻辑门，并且（ii）每个逻辑门仅允许一个开关输入。在某些情况下，可以通过在三个不同的电源域分配逻辑门来进一步降低抖动。换句话说，逻辑门输入可以通过门控其自身功率域中的每个信号来进一步隔离。此外，多路复用器电路通过利用三个基本相同的逻辑门来提供内置的延迟匹配。

8. 发明授权

US06553503B1 Circuitry, architecture and method(s) for synchronizing data 有权
公开(公告)号：US06553503B1
公开(公告)日：2003-04-22
申请号：US09391865
申请日：1999-09-08
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： G06F104
CPC分类号： H04J3/0626 , G06F5/14 , H04L7/04 , H04L25/14
摘要： An apparatus comprising a first programmable circuit configured to present (i) a first parallel data signal and (ii) a first control signal in response to one or more serial data signals and a second programmable circuit configured to generate a second parallel data signal in response to (i) the first parallel data signal, (ii) the first control signal and (iii) a second control signal.

9. 发明授权

US06351476B2 Tunable semiconductor laser system 有权
标题翻译：可调谐半导体激光系统
公开(公告)号：US06351476B2
公开(公告)日：2002-02-26
申请号：US09761542
申请日：2001-01-16
申请人： Peter Kner , Gabriel Li , D. Philip Worland , Rang-Chen Yu , Wupen Yuen
发明人： Peter Kner , Gabriel Li , D. Philip Worland , Rang-Chen Yu , Wupen Yuen
IPC分类号： H01S310
CPC分类号： H01S5/06804 , H01L2224/48091 , H01L2924/16195 , H01S5/0078 , H01S5/02248 , H01S5/0687 , H01S5/18366 , H01L2924/00014
摘要： A tunable semiconductor laser system includes a laser with a semiconductor active region positioned between upper and lower confining regions of opposite type semiconductor material. First and second reflective members are positioned at opposing edges of the active and confining regions. A wavelength tuning member and a temperature sensor are coupled to the laser. A control loop is coupled to the temperature sensor and the tuning member. In response to a detected change in temperature the control loop sends an adjustment signal to the tuning member and the tuning member adjusts a voltage or current supplied to the laser to provide a controlled output beam of selected wavelength.
摘要翻译：可调谐半导体激光器系统包括具有半导体有源区域的激光器，该半导体有源区域位于相对的半导体材料的上部和下部约束区域之间。第一和第二反射构件定位在活动和限制区域的相对边缘处。波长调谐构件和温度传感器耦合到激光器。控制回路耦合到温度传感器和调谐构件。响应于检测到的温度变化，控制回路向调谐构件发送调整信号，并且调谐构件调节提供给激光器的电压或电流以提供所选波长的受控输出光束。

10. 发明授权

US5651036A Third harmonic suppression scheme for a wave used in a phase-to-frequency converter 失效
标题翻译：用于在相变频器中使用的波的三次谐波抑制方案
公开(公告)号：US5651036A
公开(公告)日：1997-07-22
申请号：US644036
申请日：1996-05-09
申请人： Wong Hee , Gabriel Li
发明人： Wong Hee , Gabriel Li
IPC分类号： H03L7/099 , H04L7/00
CPC分类号： H03L7/099
摘要： A phase-to-frequency converter uses a triangular waveform synthesizer to generate a triangular wave using both PDM and a DC modulation scheme. A 4-bit PDM and associated logic generates the PDM output waveform with polarity information and two switching waveforms that encode the DC level information to provide a resultant sum. The resulting waveform, after filtering, is the multiple phases of the triangular waveform. The generated multiple phases of the triangular wave are then modified by reducing the ramp rate at appropriate points to suppress the third harmonic and its multiples. The ramp rate is proportional to the pulse density output of the Pulse Density Modulator. In one embodiment, the rate of the PDM output is reduced by one half during appropriate periods by gating the output by its clock, thereby reducing its density by one half during those periods.
摘要翻译：相位到频率转换器使用三角波形合成器来使用PDM和DC调制方案来产生三角波。 4位PDM和相关逻辑产生具有极性信息的PDM输出波形和用于编码直流电平信息以提供结果和的两个开关波形。滤波后的结果波形是三角波形的多个相位。然后通过在适当的点减小斜坡率来抑制三次谐波及其倍数，从而修改产生的三角波的多相。斜坡率与脉冲密度调制器的脉冲密度输出成比例。在一个实施例中，PDM输出的速率在合适的时间期间通过将输出选通其时钟来减小一半，从而在这些周期期间将其密度降低一半。

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