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1. 发明申请

US20110016374A1 SERIAL INTERFACE DEVICES, SYSTEMS AND METHODS 有权
标题翻译：串行接口设备，系统和方法
公开(公告)号：US20110016374A1
公开(公告)日：2011-01-20
申请号：US12838035
申请日：2010-07-16
申请人： Edward L. Grivna , Gabriel Li , Thinh Tran
发明人： Edward L. Grivna , Gabriel Li , Thinh Tran
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F13/4291 , G06F11/1016
摘要： A serial interface device may include a plurality of serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values.
摘要翻译：串行接口设备可以包括多个串行链路连接，其至少在不同的串行链路连接上接收地址值和至少一个错误检测码（EDC），EDC至少从地址值生成。

2. 发明授权

US08464145B2 Serial interface devices, systems and methods 有权
标题翻译：串行接口设备，系统和方法
公开(公告)号：US08464145B2
公开(公告)日：2013-06-11
申请号：US12838035
申请日：2010-07-16
申请人： Edward L. Grivna , Gabriel Li , Thinh Tran
发明人： Edward L. Grivna , Gabriel Li , Thinh Tran
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F13/4291 , G06F11/1016
摘要： A serial interface device includes multiple serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values, the serial link connections for the address values and EDC operated separately from one another; and multiple output serial links, at least a first one of the output serial links outputting data values read from memory locations corresponding to the address values, and at least a second one of the output serial links different from and operated separately from the first one outputting EDC values generated for the data values read from the memory locations.
摘要翻译：串行接口设备包括多个串行链路连接，其至少在不同的串行链路连接上接收地址值和至少一个错误检测码（EDC），从至少地址值生成的EDC，地址值的串行链路连接以及 EDC彼此分开操作; 和多个输出串行链路，输出串行链路中的至少第一个输出从对应于地址值的存储器位置读取的数据值，以及至少第二个输出串行链路，与第一个输出串行链路不同，并且与第一个串行链路分开运行为从内存位置读取的数据值生成的EDC值。

3. 发明授权

US06944691B1 Architecture that converts a half-duplex bus to a full-duplex bus while keeping the bandwidth of the bus constant 有权
标题翻译：将半双工总线转换为全双工总线，同时保持总线带宽恒定的架构
公开(公告)号：US06944691B1
公开(公告)日：2005-09-13
申请号：US09915794
申请日：2001-07-26
申请人： Gabriel Li , Edward L. Grivna
发明人： Gabriel Li , Edward L. Grivna
IPC分类号： G06F13/42
CPC分类号： G06F13/4009
摘要： An architecture comprising a first circuit, a second circuit, and one or more pairs of communication channels. The first circuit may be configured to transmit one or more first serial streams in response to a plurality of first source data streams and recover a plurality of second source data streams from one or more second serial streams. The second circuit may be configured to transmit the one or more second serial streams in response to the plurality of second source data streams and recover the plurality of first source data streams in response to the one or more first serial streams. The first circuit and the second circuit may be coupled by the one or more pairs of communication channels. The first and second circuits may be configured to transmit simultaneously.
摘要翻译：一种包括第一电路，第二电路和一对或多对通信信道的架构。第一电路可以被配置为响应于多个第一源数据流传输一个或多个第一串行流，并且从一个或多个第二串行流恢复多个第二源数据流。第二电路可以被配置为响应于多个第二源数据流来发送一个或多个第二串行流，并响应于一个或多个第一串行流恢复多个第一源数据流。第一电路和第二电路可以由一对或多对通信信道耦合。第一和第二电路可以被配置为同时传输。

4. 发明授权

US08095747B2 Memory system and method 有权
标题翻译：内存系统和方法
公开(公告)号：US08095747B2
公开(公告)日：2012-01-10
申请号：US12239532
申请日：2008-09-26
申请人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
发明人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
IPC分类号： G06F12/00
CPC分类号： G06F13/28
摘要： In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.
摘要翻译：在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控制器。配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

5. 发明申请

US20100082861A1 MEMORY SYSTEM AND METHOD 有权
标题翻译：记忆系统和方法
公开(公告)号：US20100082861A1
公开(公告)日：2010-04-01
申请号：US12239532
申请日：2008-09-26
申请人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
发明人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
IPC分类号： G06F13/42 , G06F13/40 , G06F13/28
CPC分类号： G06F13/28
摘要： In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.
摘要翻译：在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控制器。配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

6. 发明授权

US07876133B1 Output buffer circuit 有权
标题翻译：输出缓冲电路
公开(公告)号：US07876133B1
公开(公告)日：2011-01-25
申请号：US11904901
申请日：2007-09-27
申请人： Alan McLaughlin , Gabriel Li
发明人： Alan McLaughlin , Gabriel Li
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/018521
摘要： An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.
摘要翻译：输出驱动器电路可以包括至少第一驱动器晶体管，其具有耦合在第一电源节点和输出节点之间的源极 - 漏极路径。第一可变电流源可以产生具有与电源电压成反比的至少一个分量的电流。第一驱动器开关元件可以与至少第一驱动器晶体管的栅极和第二电源节点之间的第一可变电流源串联耦合。

7. 发明申请

US20100026345A1 CIRCUIT, SYSTEM, AND METHOD FOR MULTIPLEXING SIGNALS WITH REDUCED JITTER 有权
标题翻译：具有减少抖动信号的多路复用信号的电路，系统和方法
公开(公告)号：US20100026345A1
公开(公告)日：2010-02-04
申请号：US12577477
申请日：2009-10-12
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03K19/00 , H03K17/16
CPC分类号： H04J3/047 , H03K17/002 , H03K19/1737
摘要： An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.
摘要翻译：一种具有多个电源域和多个逻辑部件的装置。多个逻辑组件中的每一个驻留在多个电源域中的不同的一个中。所述多个逻辑部件中的每一个被配置为与所述多个电源域中的相应一个中的对应的时钟信号一起操作。

8. 发明授权

US06597707B1 Circuitry, architecture and methods for synchronizing data 有权
标题翻译：用于同步数据的电路，架构和方法
公开(公告)号：US06597707B1
公开(公告)日：2003-07-22
申请号：US09391967
申请日：1999-09-08
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H04L2536
CPC分类号： G06F5/10 , H04L7/005 , H04L7/033 , H04L7/04
摘要： An apparatus comprising a first programmable circuit configured to present (i) a first parallel data signal and (ii) a first control signal in response to one or more serial data signals and a second programmable circuit configured to generate a second parallel data signal in response to (i) the first parallel data signal, (ii) the first control signal and (iii) a second control signal.
摘要翻译：一种装置，包括第一可编程电路，其被配置为响应于一个或多个串行数据信号呈现（i）第一并行数据信号和（ii）第一控制信号，以及第二可编程电路，其被配置为响应于产生第二并行数据信号（i）第一并行数据信号，（ii）第一控制信号和（iii）第二控制信号。

9. 发明授权

US06181717B2 Tunable semiconductor laser system 有权
公开(公告)号：US06181717B2
公开(公告)日：2001-01-30
申请号：US09326010
申请日：1999-06-04
申请人： Peter Kner , Gabriel Li , Philip Worland , Rang-Chen Yu , Wupen Yuen
发明人： Peter Kner , Gabriel Li , Philip Worland , Rang-Chen Yu , Wupen Yuen
IPC分类号： H01S310
CPC分类号： H01S5/06804 , H01L2224/48091 , H01L2924/16195 , H01S5/0078 , H01S5/02248 , H01S5/0687 , H01S5/18366 , H01L2924/00014
摘要： A tunable semiconductor laser system includes a laser with a semiconductor active region positioned between upper and lower confining regions of opposite type semiconductor material. First and second reflective members are positioned at opposing edges of the active and confining regions. A wavelength tuning member and a temperature sensor are coupled to the laser. A control loop is coupled to the temperature sensor and the tuning member. In response to a detected change in temperature the control loop sends an adjustment signal to the tuning member and the tuning member adjusts a voltage or current supplied to the laser to provide a controlled output beam of selected wavelength.

10. 发明授权

US5646967A Multi-phase triangular wave synthesizer for phase-to-frequency converter 失效
标题翻译：用于相变频器的多相三角波合成器
公开(公告)号：US5646967A
公开(公告)日：1997-07-08
申请号：US644035
申请日：1996-05-09
申请人： Wong Hee , Gabriel Li
发明人： Wong Hee , Gabriel Li
IPC分类号： G06F1/02 , G06F7/62 , H03L7/08 , H03L7/089 , H04L7/00
CPC分类号： H03L7/089 , G06F1/022 , G06F7/62 , H03L7/08
摘要： A triangular waveform synthesizer for a phase-to-frequency converter generates a saw tooth and triangular wave using both PDM and a DC modulation scheme. To minimize both delay and logic, while continuing to provide reasonable resolution, a 4-bit PDM and associated logic generates the PDM output waveform with polarity information and two switching waveforms that encode the DC level information to provide a resultant sum. The resulting waveform, after filtering, is the triangular waveform. Since the switching and adding of the DC levels occurs in real time, the actual delay for the resultant triangular wave is only that of the 4-bit PDM.
摘要翻译：用于相变频率转换器的三角波形合成器使用PDM和DC调制方案来产生锯齿和三角波。为了最小化延迟和逻辑，在继续提供合理分辨率的同时，4位PDM和相关逻辑产生具有极性信息的PDM输出波形和两个编码直流电平信息的开关波形，以提供最终的和。滤波后的结果波形是三角波形。由于直流电平的切换和加法实时发生，所以产生的三角波的实际延迟只是4位PDM的延迟。

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