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    • 1. 发明授权
    • Method and apparatus for pipelined conversions in touch sensing systems
    • 触摸传感系统中流水线转换的方法和装置
    • US09405409B1
    • 2016-08-02
    • US13341285
    • 2011-12-30
    • Edward L. GrivnaHans Van AntwerpenPatrick Prendergast
    • Edward L. GrivnaHans Van AntwerpenPatrick Prendergast
    • G06F3/044G06F3/0354G06F3/041
    • G06F3/044G06F3/03547G06F3/0416
    • A touch sensing system and methods of operating the same for pipelined conversions are provided. In one embodiment, the method includes: (i) configuring a capacitive sensing system including a plurality of capacitive sensing elements for a first conversion; (ii) sensing capacitance in the capacitive sensing elements, and converting the capacitance sensed in the capacitive sensing elements to a digital, first conversion result; and (iii) while converting the capacitance sensed to the first conversion result, configuring the capacitive sensing system. In another embodiment, the capacitive sensing system includes a plurality of channels, and sensing capacitance and converting the capacitance sensed to the first conversion result includes integrating analog signals from the capacitive sensing elements for one of the plurality of channels while converting the integrated signal for another of the plurality of channels to a digital subconversion result.
    • 提供了一种触摸传感系统及其操作方法,用于流水线转换。 在一个实施例中,该方法包括:(i)配置包括用于第一转换的多个电容感测元件的电容感测系统; (ii)感测电容感测元件中的电容,以及将在电容感测元件中感测到的电容转换为数字的第一转换结果; 以及(iii)在将感测到的电容转换为第一转换结果的同时,配置电容感测系统。 在另一个实施例中,电容感测系统包括多个通道,并且感测电容并将感测的电容转换为第一转换结果包括对来自多个通道之一的电容感应元件的模拟信号进行积分,同时将另一个 的数字子转换结果。
    • 5. 发明授权
    • 8-bit to 10-bit encoding method and apparatus
    • 8位到10位编码方法和装置
    • US07518534B2
    • 2009-04-14
    • US11880163
    • 2007-07-20
    • Edward L. Grivna
    • Edward L. Grivna
    • H03M7/00
    • H03M5/145
    • Methods and systems for generating 10-bit control codes for use in 8-bit to 10-bit encoding are disclosed. Such control codes can have low subblock disparity (where subblocks include 6-bit and 4-bit blocks), limited run lengths when concatenated, limited run lengths within sub-blocks, meet minimal allowable cumulative disparity values at predetermined bit locations (not violate a transition matrix), and not form an aliased comma character sequence within a code, or when codes are concatenated with other codes or encoded data values. Preferably, new codes are added to existing 8B10B schemes with less than sixteen control codes to arrive at a control code set of at least sixteen.
    • 公开了用于产生用于8位至10位编码的10位控制代码的方法和系统。 这样的控制码可以具有低子块视差(其中子块包括6位和4位块),连接时的有限行程长度,子块内的有限行程长度,在预定位位置满足最小允许累积视差值(不违反 转换矩阵),并且不在代码中形成别名逗号字符序列,或者当代码与其他代码或编码数据值连接时。 优选地,将新的代码添加到具有少于十六个控制代码的现有8B10B方案中以得到至少十六个的控制代码集。
    • 6. 发明申请
    • 8-bit to 10-bit encoding method and apparatus
    • 8位到10位编码方法和装置
    • US20080024334A1
    • 2008-01-31
    • US11880163
    • 2007-07-20
    • Edward L. Grivna
    • Edward L. Grivna
    • H03M7/00
    • H03M5/145
    • Methods and systems for generating 10-bit control codes for use in 8-bit to 10-bit encoding are disclosed. Such control codes can have low subblock disparity (where subblocks include 6-bit and 4-bit blocks), limited run lengths when concatenated, limited run lengths within sub-blocks, meet minimal allowable cumulative disparity values at predetermined bit locations (not violate a transition matrix), and not form an aliased comma character sequence within a code, or when codes are concatenated with other codes or encoded data values. Preferably, new codes are added to existing 8B10B schemes with less than sixteen control codes to arrive at a control code set of at least sixteen.
    • 公开了用于产生用于8位至10位编码的10位控制代码的方法和系统。 这样的控制码可以具有低子块视差(其中子块包括6位和4位块),连接时的有限行程长度,子块内的有限行程长度,在预定位位置满足最小允许累积视差值(不违反 转换矩阵),并且不在代码中形成别名逗号字符序列,或者当代码与其他代码或编码数据值连接时。 优选地,将新的代码添加到具有少于十六个控制代码的现有8B10B方案中以得到至少十六个的控制代码集。
    • 8. 发明授权
    • Minimum-latency data mover with auto-segmentation and reassembly
    • 具有自动分段和重新组装的最小延迟数据移动器
    • US5949799A
    • 1999-09-07
    • US777304
    • 1996-12-27
    • Edward L. GrivnaPaul Scott
    • Edward L. GrivnaPaul Scott
    • H04L1/16H04L1/18
    • H04L1/1835H04L1/1664H04L1/1671H04L1/1874
    • A data mover which provides guaranteed transfer of data between two locations. The data mover includes a pair of data packet memories for input, a pair of data packet memories for output, and a controller which alternately switches each of the paired data packet memories between a data loading mode and a data unloading mode. The controller enables one of the paired data packet memories in the data loading mode and enables the other one of the paired data packet memories in the data unloading mode. The controller switches the modes of the paired data packet memories upon receiving an acknowledgement of moved data. By (a) switching the paired data packet memories upon receiving the acknowledgement, (b) segmenting the data packets (enabling data transfer initiation before all source data becomes available) and/or (c) embedding a response (enabling transmission of the next packet without first waiting for complete transmission of an incoming packet), complete transmission of the bi-directional data is automatically segmented and reassembled to minimize latency.
    • 数据移动器,可在两个位置之间保证数据传输。 数据移动器包括用于输入的一对数据分组存储器,用于输出的一对数据分组存储器以及在数据加载模式和数据卸载模式之间交替切换每个配对数据分组存储器的控制器。 控制器使数据加载模式中的成对数据分组存储器中的一个能够使数据分支存储器中的另一个成为数据卸载模式。 控制器在接收到移动数据的确认后,切换配对数据包存储器的模式。 通过(a)在接收到确认时切换配对数据分组存储器,(b)分割数据分组(在所有源数据变为可用之前启用数据传输启动)和/或(c)嵌入响应(使能下一个分组的传输 没有首先等待传入分组的完整传输),双向数据的完整传输将被自动分段和重组,以最小化等待时间。
    • 10. 发明授权
    • Serial interface devices, systems and methods
    • 串行接口设备,系统和方法
    • US08464145B2
    • 2013-06-11
    • US12838035
    • 2010-07-16
    • Edward L. GrivnaGabriel LiThinh Tran
    • Edward L. GrivnaGabriel LiThinh Tran
    • G06F11/00H03M13/00
    • G06F13/4291G06F11/1016
    • A serial interface device includes multiple serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values, the serial link connections for the address values and EDC operated separately from one another; and multiple output serial links, at least a first one of the output serial links outputting data values read from memory locations corresponding to the address values, and at least a second one of the output serial links different from and operated separately from the first one outputting EDC values generated for the data values read from the memory locations.
    • 串行接口设备包括多个串行链路连接,其至少在不同的串行链路连接上接收地址值和至少一个错误检测码(EDC),从至少地址值生成的EDC,地址值的串行链路连接以及 EDC彼此分开操作; 和多个输出串行链路,输出串行链路中的至少第一个输出从对应于地址值的存储器位置读取的数据值,以及至少第二个输出串行链路,与第一个输出串行链路不同,并且与第一个串行链路分开运行 为从内存位置读取的数据值生成的EDC值。