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1. 发明授权

US07112497B2 Multi-layer reducible sidewall process 有权
标题翻译：多层减薄侧壁工艺
公开(公告)号：US07112497B2
公开(公告)日：2006-09-26
申请号：US10877153
申请日：2004-06-25
申请人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
发明人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/517 , H01L29/6656 , H01L29/7833
摘要： The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed (124) alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced (132) to establish second sidewall spacers having second widths which are smaller than the first widths. The smaller second sidewall spacers facilitate compliance with design rules by allowing source and drain contacts to be formed closer to the gate structure.
摘要翻译：本发明涉及一种多层侧壁工艺（100），其有助于以允许遵守某些设计规则的方式形成晶体管，同时减轻与形成彼此靠近的晶体管的区域相关联的不利影响。具有第一宽度的第一侧壁间隔物与晶体管的栅极结构一起形成（124），以便于将源极/漏极掺杂剂远离栅极结构注入足够远，使得掺杂剂原子不可能迁移到栅极结构下方的沟道区域中。另外，该工艺为掺杂剂原子提供均匀的层以通过，以减轻跨晶片的器件特性的变化。形成侧壁间隔物的方式也允许简化自对准硅化物封堵过程。随后减小第一侧壁间隔物（132）以建立具有小于第一宽度的第二宽度的第二侧壁间隔物。较小的第二侧壁间隔件通过允许源极和漏极接触形成得更靠近栅极结构而促进了设计规则的符合性。

2. 发明申请

US20050287751A1 Multi-layer reducible sidewall process 有权
标题翻译：多层减薄侧壁工艺
公开(公告)号：US20050287751A1
公开(公告)日：2005-12-29
申请号：US10877153
申请日：2004-06-25
申请人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
发明人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
IPC分类号： H01L21/302 , H01L21/336 , H01L21/461 , H01L29/51 , H01L29/78
CPC分类号： H01L29/6653 , H01L29/517 , H01L29/6656 , H01L29/7833
摘要： The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed (124) alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced (132) to establish second sidewall spacers having second widths which are smaller than the first widths. The smaller second sidewall spacers facilitate compliance with design rules by allowing source and drain contacts to be formed closer to the gate structure.
摘要翻译：本发明涉及一种多层侧壁工艺（100），其有助于以允许遵守某些设计规则的方式形成晶体管，同时减轻与形成彼此靠近的晶体管的区域相关联的不利影响。具有第一宽度的第一侧壁间隔物与晶体管的栅极结构一起形成（124），以便于将源极/漏极掺杂剂远离栅极结构注入足够远，使得掺杂剂原子不可能迁移到栅极结构下方的沟道区域中。另外，该工艺为掺杂剂原子提供均匀的层以通过，以减轻跨晶片的器件特性的变化。形成侧壁间隔物的方式也允许简化自对准硅化物封堵过程。随后减小第一侧壁间隔物（132）以建立具有小于第一宽度的第二宽度的第二侧壁间隔物。较小的第二侧壁间隔件通过允许源极和漏极接触形成得更靠近栅极结构而促进了设计规则的符合性。

3. 发明授权

US07045410B2 Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) 有权
标题翻译：使用浅沟槽隔离（STI）设计或调制CMOS晶体管阈值电压的方法
公开(公告)号：US07045410B2
公开(公告)日：2006-05-16
申请号：US10899844
申请日：2004-07-27
申请人： Freidoon Mehrad , Amitava Chatterjee
发明人： Freidoon Mehrad , Amitava Chatterjee
IPC分类号： H01L21/762 , H01L21/8238
CPC分类号： H01L21/823878 , H01L21/76237
摘要： A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is then performed (214), followed by forming an isolation trench (216) in the semiconductor body associated with the isolation opening. The isolation trench is then filled with a dielectric material (218).
摘要翻译：公开了形成隔离结构的方法（200），并且包括在半导体本体上形成具有与其相关联的隔离开口的图案化隔离硬掩模层（206,212）。然后进行到隔离开口中的注入（214），随后在与隔离开口相关联的半导体主体中形成隔离沟槽（216）。隔离沟槽然后用电介质材料（218）填充。

4. 发明申请

US20060024911A1 Method to design for or modulate the CMOS transistor inverse narrow width effect (INWE) using shallow trench isolation (STI) 有权
标题翻译：使用浅沟槽隔离（STI）设计或调制CMOS晶体管反向窄宽度效应（INWE）的方法
公开(公告)号：US20060024911A1
公开(公告)日：2006-02-02
申请号：US10899844
申请日：2004-07-27
申请人： Freidoon Mehrad , Amitava Chatterjee
发明人： Freidoon Mehrad , Amitava Chatterjee
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76237
摘要： A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is then performed (214), followed by forming an isolation trench (216) in the semiconductor body associated with the isolation opening. The isolation trench is then filled with a dielectric material (218).
摘要翻译：公开了形成隔离结构的方法（200），并且包括在半导体本体上形成具有与其相关联的隔离开口的图案化隔离硬掩模层（206,212）。然后进行到隔离开口中的注入（214），随后在与隔离开口相关联的半导体主体中形成隔离沟槽（216）。隔离沟槽然后用电介质材料（218）填充。

5. 发明授权

US07448395B2 Process method to facilitate silicidation 有权
标题翻译：硅化方法
公开(公告)号：US07448395B2
公开(公告)日：2008-11-11
申请号：US10894374
申请日：2004-07-19
申请人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
发明人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
IPC分类号： B08B6/00 , C25F1/00 , C25F3/30 , C25F5/00
CPC分类号： H01L21/28518 , H01L21/02046 , H01L21/0206 , H01L21/28052 , H01L29/665
摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.
摘要翻译：本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

6. 发明申请

US20060014393A1 Process method to facilitate silicidation 有权
标题翻译：硅化方法
公开(公告)号：US20060014393A1
公开(公告)日：2006-01-19
申请号：US10894374
申请日：2004-07-19
申请人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
发明人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
IPC分类号： H01L21/302
CPC分类号： H01L21/28518 , H01L21/02046 , H01L21/0206 , H01L21/28052 , H01L29/665
摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.
摘要翻译：本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

7. 发明申请

US20110031557A1 GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM 有权
标题翻译：门式电介质第一次更换门电路及集成电路
公开(公告)号：US20110031557A1
公开(公告)日：2011-02-10
申请号：US12908140
申请日：2010-10-20
申请人： Brian K. Kirkpatrick , Freidoon Mehrad , Shaofeng Yu
发明人： Brian K. Kirkpatrick , Freidoon Mehrad , Shaofeng Yu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L29/513 , H01L29/66545 , H01L29/66553 , H01L29/6656
摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.
摘要翻译：一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。栅极电介质层形成在PMOS区域和NMOS区域上。在栅极电介质层上形成原始栅电极层。栅极掩模层被施加在栅极电极层上。蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。为PMOS器件和NMOS器件形成源极和漏极区域。为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

8. 发明授权

US07601575B2 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance 有权
标题翻译：用于改善晶体管性能的前S / D退火选择性氮化物/氧化物复合帽的集成
公开(公告)号：US07601575B2
公开(公告)日：2009-10-13
申请号：US11072779
申请日：2005-03-04
申请人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
发明人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/44
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , Y10S438/902
摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.
摘要翻译：本发明通过提供一种提高沟道电子迁移率而不会使PMOS晶体管器件基本上衰减的帽退火工艺来促进半导体器件的操作和制造。该方法使用氧化物/氮化物复合帽来改变通道区域上的活性掺杂剂分布。在退火过程中，掺杂剂在沟道区中迁移出Si / SiO 2，从而改变沟道区的掺杂物分布。这种改变的形状通常改善了沟道迁移率，从而提高了晶体管的性能并允许更小的密度设计。

9. 发明申请

US20090050976A1 PROCESS METHOD TO FULLY SALICIDE (FUSI) BOTH N-POLY AND P-POLY ON A CMOS FLOW 有权
标题翻译：在CMOS流程上充分浸出（FUSI）N-POLY和P-POLY的方法
公开(公告)号：US20090050976A1
公开(公告)日：2009-02-26
申请号：US11844832
申请日：2007-08-24
申请人： Freidoon Mehrad , Frank S. Johnson
发明人： Freidoon Mehrad , Frank S. Johnson
IPC分类号： H01L21/3205 , H01L29/78
CPC分类号： H01L21/823835
摘要： An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming a first silicide in at least a top portion of a gate electrode of the PMOS devices and not over the NMOS devices. The method further comprises concurrently forming a second silicide in at least a top portion of a gate electrode of both the NMOS and PMOS devices, and forming a FUSI gate silicide of the gate electrodes. In one embodiment, the thickness of the second silicide is greater than the first silicide by an amount which compensates for a difference in the rates of silicide formation between the NMOS and PMOS devices.
摘要翻译：公开了在相同MOS器件的NMOS和PMOS晶体管中形成完全硅化（FUSI）栅极的改进方法。在一个示例中，该方法包括在PMOS器件的栅电极的至少顶部部分中形成第一硅化物，而不是在NMOS器件上形成。该方法还包括在NMOS和PMOS器件的栅电极的至少顶部中同时形成第二硅化物，以及形成栅电极的FUSI栅极硅化物。在一个实施例中，第二硅化物的厚度大于第一硅化物的量，该量补偿了NMOS和PMOS器件之间的硅化物形成速率的差异。

10. 发明申请

US20080265344A1 METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE 有权
标题翻译：同时硅化多晶硅栅极和半导体器件的源极/漏极的方法及相关器件
公开(公告)号：US20080265344A1
公开(公告)日：2008-10-30
申请号：US11741519
申请日：2007-04-27
申请人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
发明人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
摘要翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及活跃区域。

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