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1. 发明授权

US09035399B2 Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a semiconductor device 有权
标题翻译：用于促进半导体器件的多晶硅栅极和源极/漏极的同时硅化的结构
公开(公告)号：US09035399B2
公开(公告)日：2015-05-19
申请号：US12731932
申请日：2010-03-25
申请人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
发明人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
IPC分类号： H01L29/78 , H01L29/66 , H01L21/28 , H01L21/8238 , H01L29/49
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
摘要翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及活跃区域。

2. 发明申请

US20080265344A1 METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE 有权
标题翻译：同时硅化多晶硅栅极和半导体器件的源极/漏极的方法及相关器件
公开(公告)号：US20080265344A1
公开(公告)日：2008-10-30
申请号：US11741519
申请日：2007-04-27
申请人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
发明人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
摘要翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及活跃区域。

3. 发明申请

US20100176462A1 METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE 审中-公开
标题翻译：同时硅化多晶硅栅极和半导体器件的源极/漏极的方法及相关器件
公开(公告)号：US20100176462A1
公开(公告)日：2010-07-15
申请号：US12731932
申请日：2010-03-25
申请人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
发明人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
IPC分类号： H01L29/78
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
摘要翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及活跃区域。

4. 发明授权

US07727842B2 Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device 有权
标题翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法及相关器件
公开(公告)号：US07727842B2
公开(公告)日：2010-06-01
申请号：US11741519
申请日：2007-04-27
申请人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
发明人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
IPC分类号： H01L21/8234
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
摘要翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及活跃区域。

5. 发明授权

US07396716B2 Method to obtain fully silicided poly gate 有权
标题翻译：获得完全硅化多孔的方法
公开(公告)号：US07396716B2
公开(公告)日：2008-07-08
申请号：US11201924
申请日：2005-08-11
申请人： Freidoon Mehrad , Shaofeng Yu , Joe G. Tran
发明人： Freidoon Mehrad , Shaofeng Yu , Joe G. Tran
IPC分类号： H01L21/311
CPC分类号： H01L21/823425 , H01L21/28097 , H01L21/31111 , H01L21/31116 , H01L21/823443 , H01L21/823468 , H01L21/823835 , H01L29/4975 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.
摘要翻译：本发明提供一种制造微电子器件的方法。在一个方面，该方法包括在位于微电子器件衬底210之上的栅极结构230上形成覆盖层610，其中栅极结构230包括侧壁间隔物515并且具有位于它们之间的掺杂区域525。保护层710放置在覆盖层610和掺杂区域525之上，并且去除位于栅极结构上方的保护层710和覆盖层610的一部分以露出栅极结构230的顶表面。保护层710和覆盖层610的剩余部分保留在掺杂区域525之上。在栅极结构230的顶表面暴露的情况下，将金属结合到栅极结构中以形成栅电极230。

6. 发明授权

US07732313B2 FUSI integration method using SOG as a sacrificial planarization layer 有权
标题翻译：使用SOG作为牺牲平坦化层的FUSI积分方法
公开(公告)号：US07732313B2
公开(公告)日：2010-06-08
申请号：US12348660
申请日：2009-01-05
申请人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
发明人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
IPC分类号： H01L21/44
CPC分类号： H01L21/31055 , H01L21/28097 , H01L21/32134 , H01L29/4975 , H01L29/6656 , H01L29/7833
摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
摘要翻译：一种制造晶体管20的方法，其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除它。

7. 发明授权

US07498264B2 Method to obtain fully silicided poly gate 有权
标题翻译：获得完全硅化多孔的方法
公开(公告)号：US07498264B2
公开(公告)日：2009-03-03
申请号：US11176725
申请日：2005-07-07
申请人： Freidoon Mehard , Shafoeng Yu , Joe G. Tran
发明人： Freidoon Mehard , Shafoeng Yu , Joe G. Tran
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/28097 , H01L29/4975 , H01L29/6656 , H01L29/6659
摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a spacer material 160 over gate electrodes 150 that are, in turn, located over a microelectronics substrate 110. The gate electrodes 150 have a doped region 170a located between them. A portion of the spacer material 160 is removed with a chemical/mechanical process using a slurry that is selective to a portion of the spacer material 160. The method further comprises etching a remaining portion of the spacer material 163, 165, 168 to form spacer sidewalls 163, 165, 168 on the gate electrodes 150. The etching exposes a surface of the gate electrodes 150 and leaves a portion of the spacer material 168 over the doped region 170a. Metal is then incorporated into the gate electrodes 150 to form silicided gate electrodes 150.
摘要翻译：本发明提供一种制造微电子器件的方法。在一个方面，该方法包括在栅电极150上形成间隔物材料160，栅极150又位于微电子基板110上方。栅电极150具有位于它们之间的掺杂区域170a。使用对间隔材料160的一部分有选择性的浆料，通过化学/机械方法去除间隔物材料160的一部分。该方法还包括蚀刻间隔物材料163,165,168的剩余部分以形成间隔物在栅极电极150上的侧壁163,165,168。蚀刻暴露出栅电极150的表面，并将间隔材料168的一部分留在掺杂区域170a上。然后将金属结合到栅电极150中以形成硅化栅电极150。

8. 发明授权

US07943499B2 FUSI integration method using SOG as a sacrificial planarization layer 有权
标题翻译：使用SOG作为牺牲平坦化层的FUSI积分方法
公开(公告)号：US07943499B2
公开(公告)日：2011-05-17
申请号：US12603169
申请日：2009-10-21
申请人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
发明人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L21/31055 , H01L21/28097 , H01L21/32134 , H01L29/4975 , H01L29/6656 , H01L29/7833
摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
摘要翻译：一种制造晶体管20的方法，其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除它。

9. 发明授权

US07732312B2 FUSI integration method using SOG as a sacrificial planarization layer 有权
公开(公告)号：US07732312B2
公开(公告)日：2010-06-08
申请号：US11338028
申请日：2006-01-24
申请人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
发明人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
IPC分类号： H01L21/44
CPC分类号： H01L21/31055 , H01L21/28097 , H01L21/32134 , H01L29/4975 , H01L29/6656 , H01L29/7833
摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

10. 发明申请

US20100041231A1 FUSI Integration Method Using SOG as a Sacrificial Planarization Layer 有权
标题翻译：使用SOG作为牺牲平面化层的FUSI集成方法
公开(公告)号：US20100041231A1
公开(公告)日：2010-02-18
申请号：US12603169
申请日：2009-10-21
申请人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
发明人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
IPC分类号： H01L21/30
CPC分类号： H01L21/31055 , H01L21/28097 , H01L21/32134 , H01L29/4975 , H01L29/6656 , H01L29/7833
摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
摘要翻译：一种制造晶体管20的方法，其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除。

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