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1. 发明授权

US08053296B2 Capacitor formed on a recrystallized polysilicon layer 有权
标题翻译：在再结晶的多晶硅层上形成的电容器
公开(公告)号：US08053296B2
公开(公告)日：2011-11-08
申请号：US12478512
申请日：2009-06-04
申请人： Jiong-Ping Lu , Haowen Bu , Clint Montgomery
发明人： Jiong-Ping Lu , Haowen Bu , Clint Montgomery
IPC分类号： H01L21/00
CPC分类号： H01L28/40 , H01L27/1085
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer 148 located over a gate electrode layer 143, a capacitor 170 located on the recrystallized polysilicon layer 148. The capacitor 170, in this embodiment, includes a first electrode 173, an insulator 175 located over the first electrode 173, and a second electrode 178 located over the insulator 175.
摘要翻译：本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。除了其他元件之外，半导体器件包括位于栅电极层143上的再结晶多晶硅层148，位于再结晶多晶硅层148上的电容器170.在该实施例中，电容器170包括第一电极173，绝缘体175 位于第一电极173上方，以及位于绝缘体175上方的第二电极178。

2. 发明申请

US20100159665A1 CAPACITOR FORMED ON A RECRYSTALLIZED POLYSILICON LAYER 有权
标题翻译：电容器在重组多晶硅层上形成
公开(公告)号：US20100159665A1
公开(公告)日：2010-06-24
申请号：US12478512
申请日：2009-06-04
申请人： Jiong-Ping Lu , Haowen Bu , Clint Montgomery
发明人： Jiong-Ping Lu , Haowen Bu , Clint Montgomery
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L27/1085
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer 148 located over a gate electrode layer 143, a capacitor 170 located on the recrystallized polysilicon layer 148. The capacitor 170, in this embodiment, includes a first electrode 173, an insulator 175 located over the first electrode 173, and a second electrode 178 located over the insulator 175.
摘要翻译：本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。除了其他元件之外，半导体器件包括位于栅电极层143上的再结晶多晶硅层148，位于再结晶多晶硅层148上的电容器170.在该实施例中，电容器170包括第一电极173，绝缘体175 位于第一电极173上方，以及位于绝缘体175上方的第二电极178。

3. 发明申请

US20060024882A1 Method for manufacturing a semiconductor device having silicided regions 有权
标题翻译：制造具有硅化物区域的半导体器件的方法
公开(公告)号：US20060024882A1
公开(公告)日：2006-02-02
申请号：US10901756
申请日：2004-07-29
申请人： Jiong-Ping Lu , Clint Montgomery , Lindsey Hall , Donald Miles , Duofeng Yue , Thomas Bonifield
发明人： Jiong-Ping Lu , Clint Montgomery , Lindsey Hall , Donald Miles , Duofeng Yue , Thomas Bonifield
IPC分类号： H01L21/336
CPC分类号： H01L21/823835 , H01L21/02057 , H01L21/0206 , H01L21/02068 , H01L27/0629 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).
摘要翻译：本发明提供一种半导体器件的制造方法以及包括该半导体器件的集成电路的制造方法。除了其他步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成栅极结构（120）并且在栅极结构（120）附近的衬底（110）中形成源极/漏极区域（190））。该方法还包括对栅极结构（120）和衬底（110）进行干蚀刻工艺，并且在将栅极结构（120）和衬底（120）经受栅极结构（120）和衬底（110）到干蚀刻工艺。此后，该方法包括在栅极结构（120）和氟化源极/漏极（320）中形成金属硅化物区域（510,520）。

4. 发明申请

US20060014393A1 Process method to facilitate silicidation 有权
标题翻译：硅化方法
公开(公告)号：US20060014393A1
公开(公告)日：2006-01-19
申请号：US10894374
申请日：2004-07-19
申请人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
发明人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
IPC分类号： H01L21/302
CPC分类号： H01L21/28518 , H01L21/02046 , H01L21/0206 , H01L21/28052 , H01L29/665
摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.
摘要翻译：本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

5. 发明申请

US20050090115A1 Post plasma clean process for a hardmask 有权
公开(公告)号：US20050090115A1
公开(公告)日：2005-04-28
申请号：US10692609
申请日：2003-10-24
申请人： Brian Kirkpatrick , Clint Montgomery , Brian Trentman , Randall Pak
发明人： Brian Kirkpatrick , Clint Montgomery , Brian Trentman , Randall Pak
IPC分类号： B08B7/00 , H01L21/02 , H01L21/304 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/76 , H01L21/762 , H01L21/302
CPC分类号： H01L21/02054 , H01L21/02063 , H01L21/31111 , H01L21/76224
摘要： The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes plasma etching 250 through a patterned hardmask layer 210 located over a semiconductor substrate 225 wherein the plasma etching forms a modified layer 210a on the hardmask layer 210, and removing at least a substantial portion of the modified layer 210a by exposing the modified layer 210a to a post plasma clean process.

6. 发明申请

US20090170258A1 METHODS FOR FULL GATE SILICIDATION OF METAL GATE STRUCTURES 有权
标题翻译：金属门结构的全栅硅酸盐化方法
公开(公告)号：US20090170258A1
公开(公告)日：2009-07-02
申请号：US11965024
申请日：2007-12-27
申请人： Aaron Frank , David Gonzalez, JR. , Mark R. Visokay , Clint Montgomery
发明人： Aaron Frank , David Gonzalez, JR. , Mark R. Visokay , Clint Montgomery
IPC分类号： H01L21/8238 , H01L21/28
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823864 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.
摘要翻译：一个实施例涉及一种制造集成电路的方法。在该方法中，p型多晶硅设置在半导体本体上，其中p型多晶硅具有从p型多晶硅的顶表面测量的第一深度。将n型掺杂剂注入到p型多晶硅中以在p型多晶硅的顶表面上形成反掺杂层，其中反掺杂层具有小于第一深度的第二深度。提供催化剂金属，其与反掺杂层相结合以形成催化剂表面。金属沉积在催化剂表面上。进行热处理，其在催化剂表面存在下使金属与p型多晶硅反应形成金属硅化物。还公开了其它方法和装置。

7. 发明授权

US07448395B2 Process method to facilitate silicidation 有权
标题翻译：硅化方法
公开(公告)号：US07448395B2
公开(公告)日：2008-11-11
申请号：US10894374
申请日：2004-07-19
申请人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
发明人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
IPC分类号： B08B6/00 , C25F1/00 , C25F3/30 , C25F5/00
CPC分类号： H01L21/28518 , H01L21/02046 , H01L21/0206 , H01L21/28052 , H01L29/665
摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.
摘要翻译：本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

8. 发明授权

US07422968B2 Method for manufacturing a semiconductor device having silicided regions 有权
标题翻译：制造具有硅化物区域的半导体器件的方法
公开(公告)号：US07422968B2
公开(公告)日：2008-09-09
申请号：US10901756
申请日：2004-07-29
申请人： Jiong-Ping Lu , Clint Montgomery , Lindsey Hall , Donald Miles , Duofeng Yue , Thomas D. Bonifiield
发明人： Jiong-Ping Lu , Clint Montgomery , Lindsey Hall , Donald Miles , Duofeng Yue , Thomas D. Bonifiield
IPC分类号： H01L21/425
CPC分类号： H01L21/823835 , H01L21/02057 , H01L21/0206 , H01L21/02068 , H01L27/0629 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).
摘要翻译：本发明提供一种半导体器件的制造方法以及包括该半导体器件的集成电路的制造方法。除了其他步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成栅极结构（120）并且在栅极结构（120）附近的衬底（110）中形成源极/漏极区域（190））。该方法还包括对栅极结构（120）和衬底（110）进行干蚀刻工艺，并且在将栅极结构（120）和衬底（120）经受栅极结构（120）和衬底（110）到干蚀刻工艺。此后，该方法包括在栅极结构（120）和氟化源极/漏极（320）中形成金属硅化物区域（510,520）。

9. 发明申请

US20050146035A1 Method for forming a void free via 有权
标题翻译：形成无空隙通孔的方法
公开(公告)号：US20050146035A1
公开(公告)日：2005-07-07
申请号：US11053313
申请日：2005-02-07
申请人： Alfred Griffin , Adel El Sayed , John Campbell , Clint Montgomery
发明人： Alfred Griffin , Adel El Sayed , John Campbell , Clint Montgomery
IPC分类号： H01L21/768 , H01L23/48 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/7685 , H01L21/76858 , H01L21/76871 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.
摘要翻译：描述了多层金属和通孔结构。金属导体包括基底或种子层，体导体层，覆盖层和阻挡层，并且通孔结构包括种子层，扩散阻挡层和金属插塞。通孔种子层被控制到阻止通孔种子层和体导体层之间的反应的厚度。反应可能导致在通孔底部形成有害空隙，并且是由于通孔种子金属通过阻挡层中的开口与体导体接触而引起的。

10. 发明授权

US07863192B2 Methods for full gate silicidation of metal gate structures 有权
标题翻译：金属门结构的全栅极硅化方法
公开(公告)号：US07863192B2
公开(公告)日：2011-01-04
申请号：US11965024
申请日：2007-12-27
申请人： Aaron Frank , David Gonzalez, Jr. , Mark R. Visokay , Clint Montgomery
发明人： Aaron Frank , David Gonzalez, Jr. , Mark R. Visokay , Clint Montgomery
IPC分类号： H01L21/44
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823864 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.
摘要翻译：一个实施例涉及一种制造集成电路的方法。在该方法中，p型多晶硅设置在半导体本体上，其中p型多晶硅具有从p型多晶硅的顶表面测量的第一深度。将n型掺杂剂注入到p型多晶硅中以在p型多晶硅的顶表面上形成反掺杂层，其中反掺杂层具有小于第一深度的第二深度。提供催化剂金属，其与反掺杂层相结合以形成催化剂表面。金属沉积在催化剂表面上。进行热处理，其在催化剂表面存在下使金属与p型多晶硅反应形成金属硅化物。还公开了其它方法和装置。

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