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1. 发明授权

US06626196B2 Arrangement and method for degassing small-high aspect ratio drilled holes prior to wet chemical processing 失效
标题翻译：在湿化学处理之前排气和排气方法比较小的高比例钻孔
公开(公告)号：US06626196B2
公开(公告)日：2003-09-30
申请号：US09882235
申请日：2001-06-15
申请人： Francis J. Downes, Jr. , Raymond T. Galasco , Lawrence P. Lehman , Robert D. Topa
发明人： Francis J. Downes, Jr. , Raymond T. Galasco , Lawrence P. Lehman , Robert D. Topa
IPC分类号： B08B312
CPC分类号： H05K3/0088 , B01D19/0068 , B01D19/0078 , B08B3/12 , C23C18/1851 , Y10S134/902 , Y10S438/906
摘要： An arrangement and method for the degassing small high-aspect ratio drilled holes or vias which are present in panels such as printed circuit boards prior to wet chemical processing, including copper plating of the vias, in order to remove any air or gas bubbles from the vias tending to inhibit the reliable plating thereof. This is carried out through the utilization of an ultrasonic prewetting in a liquid bath preceding cleaning for the electroless plating process, thereby enabling all of the vias or holes to be degassed; in effect, having air removed and the vias or holes filled with liquid; thereby allowing subsequent process cleansing solutions to easily flow into the respective holes or vias in order to facilitate the electroless copper plating process.
摘要翻译：用于在湿化学处理（包括通孔的铜电镀）之前存在于诸如印刷电路板的面板中的小的高深度比钻孔或通孔的排气和方法，以便从所述孔中除去任何空气或气泡趋向于抑制其可靠电镀的通孔。这通过在清洁化学镀处理之前的液槽中利用超声预润湿来进行，从而使所有的通孔或孔被脱气; 实际上，除去空气和填充有液体的通孔或孔; 从而允许随后的工艺清洁溶液容易地流入相应的孔或通孔，以便于无电镀铜处理。

2. 发明授权

US06720502B1 Integrated circuit structure 有权
公开(公告)号：US06720502B1
公开(公告)日：2004-04-13
申请号：US09571611
申请日：2000-05-15
申请人： David J. Alcoe , Francis J. Downes, Jr. , Gerald W. Jones , John S. Kresge , Cheryl L. Tytran-Palomaki
发明人： David J. Alcoe , Francis J. Downes, Jr. , Gerald W. Jones , John S. Kresge , Cheryl L. Tytran-Palomaki
IPC分类号： H01R1204
CPC分类号： H01L23/49827 , H01L23/49822 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H05K3/4602 , H05K3/4641 , H05K2201/0215 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H01L2924/00
摘要： A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.

3. 发明授权

US06429384B1 Chip C4 assembly improvement using magnetic force and adhesive 失效
标题翻译：芯片C4组装改进使用磁力和粘合剂
公开(公告)号：US06429384B1
公开(公告)日：2002-08-06
申请号：US09588836
申请日：2000-06-07
申请人： Francis J. Downes, Jr. , Robert M. Japp , Mark V. Pierson
发明人： Francis J. Downes, Jr. , Robert M. Japp , Mark V. Pierson
IPC分类号： H05K116
CPC分类号： H01L24/81 , B23K2101/40 , H01L2224/81801 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H05K3/303 , H05K3/3436 , Y10T29/4913 , Y10T29/53196
摘要： A structure that adhesively couples a chip to an organic chip carrier. The chip is attached to a top surface of the organic chip carrier by interfacing a solder bump between a C4 solder structure on the chip and a pad on a top surface of the chip carrier. The melting temperature of the solder bump is less than the melting temperature of the C4 solder structure. A block of ferrous material is on a top surface of the chip. A temporary or permanent stiffener of ferrous material is on the top surface of the chip carrier. A permanent magnet is coupled to a bottom surface of the chip carrier. Alternatively, an electromagnetic could be utilized instead of the electromagnet. Due to the permanent magnet or the electromagnet, a magnetic force on the stiffener is directed toward the magnet and substantially flattens the first surface of the chip carrier. Similarly, a magnetic force on the block is directed toward the magnet such that the electronic component and the chip carrier are held in alignment. After the solder bump has been reflowed at a temperature between the melting temperature of the solder bump and the melting temperature of the C4 solder structure, the solder bump is reconfigured. The magnetic force on the block frictionally clamps the reflowed solder between the C4 solder structure and the pad. After the chip and carrier are cooled, the C4 solder structure is adhesively and conductively coupled to the pad.
摘要翻译：将芯片与有机芯片载体粘接的结构。芯片通过在芯片上的C4焊料结构和芯片载体的顶表面上的焊盘之间接合焊料凸块来附接到有机芯片载体的顶表面。焊料凸点的熔化温度小于C4焊料结构的熔化温度。铁质材料块在芯片的顶表面上。铁质材料的临时或永久性加强件位于芯片载体的顶表面上。永磁体耦合到芯片载体的底表面。或者，可以使用电磁来代替电磁体。由于永磁体或电磁体，加强件上的磁力被引向磁体并且基本平坦化芯片载体的第一表面。类似地，块上的磁力指向磁体，使得电子部件和芯片载体保持对准。在焊料凸块的熔化温度和C4焊料结构的熔化温度之间的温度下回流焊料凸点之后，重新配置焊料凸点。块上的磁力摩擦地夹住C4焊料结构和焊盘之间的回流焊料。在芯片和载体被冷却之后，C4焊料结构粘合地并且导电地耦合到焊盘。

4. 发明授权

US06176985B1 Laminated electroplating rack and connection system for optimized plating 失效
标题翻译：层压电镀机架和连接系统，优化电镀
公开(公告)号：US06176985B1
公开(公告)日：2001-01-23
申请号：US09178084
申请日：1998-10-23
申请人： Francis J. Downes, Jr. , Raymond Thomas Galasco , Robert Maynard Japp , John Frank Surowka
发明人： Francis J. Downes, Jr. , Raymond Thomas Galasco , Robert Maynard Japp , John Frank Surowka
IPC分类号： C25D1704
CPC分类号： C25D17/08 , H05K3/241
摘要： An electroplating apparatus provides high current electrical connections in a small area to a workpiece. The contact area may use a dendrite surface to improve the connection. An insulative gasket prevents electroplating fluids from entering the region about the contact area. A heavy core laminated within a supporting structure provides uniform current distribution of high electrical currents to the dendrite covered contact areas.
摘要翻译：电镀设备在小面积上向工件提供高电流电连接。接触区域可以使用枝晶表面来改善连接。绝缘垫片防止电镀液体进入接触区域周围的区域。层叠在支撑结构内的重芯提供了高电流到枝晶覆盖接触区域的均匀电流分布。

5. 发明授权

US06693031B2 Formation of a metallic interlocking structure 失效
标题翻译：形成金属互锁结构
公开(公告)号：US06693031B2
公开(公告)日：2004-02-17
申请号：US10039710
申请日：2002-01-04
申请人： Gerald G. Advocate, Jr. , Francis J. Downes, Jr. , Luis J. Matienzo , Ronald A. Kaschak , John S. Kresge , Daniel C. Van Hart
发明人： Gerald G. Advocate, Jr. , Francis J. Downes, Jr. , Luis J. Matienzo , Ronald A. Kaschak , John S. Kresge , Daniel C. Van Hart
IPC分类号： H01L2144
CPC分类号： H01L23/5226 , H01L23/49827 , H01L2924/0002 , H05K3/0035 , H05K3/027 , H05K3/06 , H05K3/383 , H05K3/421 , H05K3/4644 , H05K2201/0248 , H05K2201/09509 , H05K2201/09563 , H05K2203/0307 , H05K2203/0353 , H01L2924/00
摘要： An electronic structure including a metallic interlocking structure for bonding a conductive plated layer to metal surface, and a method of forming the electronic structure. The method provides a substrate having a metallic sheet within a dielectric layer. The metallic sheet includes a metal such as copper. An opening in the substrate, such as a blind via, is formed by laser drilling through the dielectric layer and partially through the metallic sheet. If the opening is a blind via, then the laser drilling is within an outer ring of the blind via cross section using a laser beam having a target diameter between about 20% and about 150% of a radius of the blind via cross section. A surface at the bottom of the opening, called a “blind surface,” includes a metallic protrusion formed by the laser drilling, such that the metallic protrusion is integral with a portion of the blind surface. The metallic protrusion includes the metal of the metallic sheet and at least one constituent element from the dielectric layer. The metallic protrusion is then etched to form a metallic interlocking structure that is integral with the portion of the blind surface. The metallic interlocking structure includes discrete metallic fibers, with each metallic fiber having a curved (or curled) geometry. Each metallic fiber has its own unique composition that includes the metal, at least one constituent element of the dielectric layer, or both.
摘要翻译：一种电子结构，包括用于将导电镀层接合到金属表面的金属互锁结构，以及形成电子结构的方法。该方法提供了在电介质层内具有金属片的衬底。金属片包括铜等金属。通过激光钻孔穿过电介质层并且部分地穿过金属片，形成诸如盲孔之类的衬底中的开口。如果开口是盲孔，则激光钻孔是通过横截面的盲孔通过横截面的半径的约20％至约150％之间的目标直径的激光束在盲孔的外环内。在开口底部的称为“盲面”的表面包括通过激光钻孔形成的金属突起，使得金属突起与盲表面的一部分成一体。金属突起包括金属片的金属和来自电介质层的至少一个构成元件。然后蚀刻金属突起以形成与盲表面的一部分成一体的金属互锁结构。金属互锁结构包括分立的金属纤维，每个金属纤维具有弯曲（或卷曲）的几何形状。每种金属纤维具有其独特的组成，其包括金属，介电层的至少一个构成元件，或两者。

6. 发明授权

US6142361A Chip C4 assembly improvement using magnetic force and adhesive 失效
标题翻译：芯片C4组装改进使用磁力和粘合剂
公开(公告)号：US6142361A
公开(公告)日：2000-11-07
申请号：US458483
申请日：1999-12-09
申请人： Francis J. Downes, Jr. , Robert M. Japp , Mark V. Pierson
发明人： Francis J. Downes, Jr. , Robert M. Japp , Mark V. Pierson
IPC分类号： H01L21/60 , H05K3/30 , H05K3/34 , B23K1/20 , B23K31/02
CPC分类号： H01L24/81 , B23K2201/40 , H01L2224/81801 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H05K3/303 , H05K3/3436 , Y10T29/4913 , Y10T29/53196
摘要： A method, and associated structure, for adhesively coupling a chip to an organic chip carrier. The chip is attached to a top surface of the organic chip carrier by interfacing a solder bump between a C4 solder structure on the chip and a pad on a top surface of the chip carrier. The melting temperature of the solder bump is less than the melting temperature of the C4 solder structure. A block of ferrous material is placed on a top surface of the chip. A temporary or permanent stiffener of ferrous material is placed on the top surface of the chip carrier. A permanent magnet is coupled to a bottom surface of the chip carrier. Alternatively, an electromagnetic could be utilized instead of the electromagnet. Due to the permanent magnet or the electromagnet, a magnetic force on the stiffener is directed toward the magnet and substantially flattens the first surface of the chip carrier. Similarly, a magnetic force on the block is directed toward the magnet such that the electronic component and the chip carrier are held in alignment. The solder bump is reflowed at a temperature between the melting temperature of the solder bump and the melting temperature of the C4 solder structure. The reflowing reconfigures the solder bump. The magnetic force on the block frictionally clamps the reflowed solder between the C4 solder structure and the pad. The chip and carrier are cooled, resulting in the C4 solder structure being adhesively and conductively coupled to the pad.
摘要翻译：一种用于将芯片粘合地耦合到有机芯片载体的方法和相关联的结构。芯片通过在芯片上的C4焊料结构和芯片载体的顶表面上的焊盘之间接合焊料凸块来附接到有机芯片载体的顶表面。焊料凸点的熔化温度小于C4焊料结构的熔化温度。将一块黑色金属材料放置在芯片的上表面上。铁芯材料的临时或永久性加强件被放置在芯片载体的顶表面上。永磁体耦合到芯片载体的底表面。或者，可以使用电磁来代替电磁体。由于永磁体或电磁体，加强件上的磁力被引向磁体并且基本平坦化芯片载体的第一表面。类似地，块上的磁力指向磁体，使得电子部件和芯片载体保持对准。在焊料凸块的熔化温度和C4焊料结构的熔化温度之间的温度下回流焊料凸点。回流重新配置焊料凸块。块上的磁力摩擦地夹住C4焊料结构和焊盘之间的回流焊料。芯片和载体被冷却，导致C4焊料结构被粘性地导电耦合到焊盘。

7. 发明授权

US06887779B2 Integrated circuit structure 失效
标题翻译：集成电路结构
公开(公告)号：US06887779B2
公开(公告)日：2005-05-03
申请号：US10719495
申请日：2003-11-21
申请人： David J. Alcoe , Francis J. Downes, Jr. , Gerald W. Jones , John S. Kresge , Cheryl L. Tytran-Palomaki
发明人： David J. Alcoe , Francis J. Downes, Jr. , Gerald W. Jones , John S. Kresge , Cheryl L. Tytran-Palomaki
IPC分类号： H01L23/498 , H05K3/46 , H01L21/4763
CPC分类号： H01L23/49827 , H01L23/49822 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H05K3/4602 , H05K3/4641 , H05K2201/0215 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H01L2924/00
摘要： A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.
摘要翻译：一种具有增加的芯片连接器和电镀通孔密度的半导体芯片载体。特别地，其中具有多个电镀通孔的基板和其上的抗疲劳再分布层。再分配层包括选择性地定位在电镀通孔上并接触电镀通孔的多个通孔。所述基板还包括接地平面，两对信号面和两对电源层，其中所述第二对电源层位于所述外部电介质层的正下方。衬底内埋入电镀通孔。

8. 发明授权

US06829823B2 Method of making a multi-layered interconnect structure 有权
标题翻译：制造多层互连结构的方法
公开(公告)号：US06829823B2
公开(公告)日：2004-12-14
申请号：US10067551
申请日：2002-02-05
申请人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
发明人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
IPC分类号： H01K310
CPC分类号： H05K3/4641 , H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/12044 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.
摘要翻译：一种制造多层互连结构的方法。第一和第二导电构件分别形成在第一和第二电介质层上。电介质层形成在导热层的相对表面上。第一和第二导电层形成在第一介电层内。第二导电层包括屏蔽信号导体并且位于第一导电层和导热层之间。通过互连结构形成的电镀通孔（PTH）电连接到第一和第二导电构件中的一个和屏蔽信号导体之一。形成在第一介电层上和第一导电构件的部分上的第三电介质层基本上覆盖在PTH上，并且包括用于提供从电子器件到屏蔽信号导体的电气路径的高密度互连层。

9. 发明授权

US5230782A Electrolytic process for reducing the organic content of an aqueous composition and apparatus therefore 失效
标题翻译：用于减少水性组合物的有机成分的电解方法及其装置
公开(公告)号：US5230782A
公开(公告)日：1993-07-27
申请号：US733662
申请日：1991-07-22
申请人： Francis J. Downes, Jr. , Oscar A. Moreno , Cindy M. Reidsema , Joseph E. Varsik
发明人： Francis J. Downes, Jr. , Oscar A. Moreno , Cindy M. Reidsema , Joseph E. Varsik
IPC分类号： C02F1/461 , C02F1/467 , C23C18/16 , C23C18/31
CPC分类号： C23C18/1617 , C02F1/4672 , C02F1/4676 , C02F1/4678 , C02F2101/18 , C02F2101/30 , C02F2209/06 , Y10S204/13
摘要： The total organic content (TOC) of an aqueous composition is reduced to 200 ppm or less by subjecting the composition to electrolysis whereby the pH of the composition at the start of the electrolysis is about 1.8 to about 7 to thereby electrolytically decompose organic materials contained in the aqueous composition.

10. 发明授权

US06373717B1 Electronic package with high density interconnect layer 有权
公开(公告)号：US06373717B1
公开(公告)日：2002-04-16
申请号：US09540172
申请日：2000-03-31
申请人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
发明人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
IPC分类号： H05K118
CPC分类号： H05K3/4641 , H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/12044 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.

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