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1. 发明授权

US07166894B2 Schottky power diode with SiCOI substrate and process for making such diode 有权
标题翻译：具有SiCOI衬底的肖特基功率二极管和用于制造这种二极管的工艺
公开(公告)号：US07166894B2
公开(公告)日：2007-01-23
申请号：US10507757
申请日：2003-03-12
申请人： François Templier , Thierry Billon , Nicolas Daval
发明人： François Templier , Thierry Billon , Nicolas Daval
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/80 , H01L31/112
CPC分类号： H01L29/6606 , H01L21/0475 , H01L21/0495 , H01L29/1608 , H01L29/78684 , H01L29/8126 , H01L29/872 , Y10S438/931
摘要： The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide (16) insulated from a solid carrier (12) by a buried layer of insulant (14), and including at least one Schottky contact between a first metal layer (40) and the surface layer of silicon carbide (16), the first metal layer (30) constituting an anode.
摘要翻译：本发明涉及一种功率接合装置，其包括具有通过绝缘体（14）的掩埋层与固体载体（12）绝缘的碳化硅层（16）的SiCOI型衬底，并且包括至少一个肖特基接触在第一金属层（40）和碳化硅（16）的表面层之间，构成阳极的第一金属层（30）。

2. 发明申请

US20050161760A1 Schottky power diode comprising a sicoi substrate and the method of producing one such diode 有权
标题翻译：肖特基功率二极管包括一个硅片基板和产生一个这样的二极管的方法
公开(公告)号：US20050161760A1
公开(公告)日：2005-07-28
申请号：US10507757
申请日：2003-03-12
申请人： Francois Templier , Thierry Billon , Nicolas Daval
发明人： Francois Templier , Thierry Billon , Nicolas Daval
IPC分类号： H01L21/04 , H01L21/338 , H01L29/24 , H01L29/47 , H01L29/786 , H01L29/812 , H01L29/872 , H01L27/095 , H01L29/15
CPC分类号： H01L29/6606 , H01L21/0475 , H01L21/0495 , H01L29/1608 , H01L29/78684 , H01L29/8126 , H01L29/872 , Y10S438/931
摘要： The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide (16) insulated from a solid carrier (12) by a buried layer of insulant (14), and including at least one Schottky contact between a first metal layer (40) and the surface layer of silicon carbide (16), the first metal layer (30) constituting an anode.
摘要翻译：本发明涉及一种功率接合装置，其包括具有通过绝缘体（14）的掩埋层与固体载体（12）绝缘的碳化硅层（16）的SiCOI型衬底，并且包括至少一个肖特基接触在第一金属层（40）和碳化硅（16）的表面层之间，构成阳极的第一金属层（30）。

3. 发明授权

US07446019B2 Method of reducing roughness of a thick insulating layer 有权
标题翻译：降低厚绝缘层粗糙度的方法
公开(公告)号：US07446019B2
公开(公告)日：2008-11-04
申请号：US11481701
申请日：2006-07-05
申请人： Nicolas Daval , Sebastien Kerdiles , Cécile Aulnette
发明人： Nicolas Daval , Sebastien Kerdiles , Cécile Aulnette
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/76254 , H01L21/31055 , H01L21/31116
摘要： A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate; treating the first substrate to form a zone of weakness beneath the insulator layer; and smoothing the exposed rough surface of the insulator layer by exposure to a gas plasma in a chamber. The chamber contains therein a gas at a pressure of greater than 0.25 Pa but less than 30 Pa, and the gas plasma is created using a radio frequency generator applying to the insulator layer a power density greater than 0.6 W/cm2 but less than 10 W/cm2 for at least 10 seconds to less than 200 seconds. Substrate bonding and layer transfer may be carried out subsequently to transfer the thin layer of substrate to the insulator layer and to a second substrate.
摘要翻译：一种通过在衬底上沉积绝缘体层来减小衬底上的绝缘体层的暴露表面的粗糙度的方法，其中绝缘体层包括与衬底相对的暴露的粗糙表面; 处理所述第一衬底以在所述绝缘体层下方形成弱化区; 以及通过暴露于室中的气体等离子体来平滑所述绝缘体层的暴露的粗糙表面。该室中含有大于0.25Pa但小于30Pa的压力的气体，并且使用射频发生器产生气体等离子体，该射频发生器施加到绝缘体层上，功率密度大于0.6W / cm 2，但小于10W / cm 2，持续至少10秒至小于200秒。衬底结合和层转移可以随后进行以将衬底的薄层转移到绝缘体层和第二衬底。

4. 发明申请

US20080132031A1 METHOD OF MANUFACTURING A SEMICONDUCTOR HETEROSTRUCTURE 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US20080132031A1
公开(公告)日：2008-06-05
申请号：US11674392
申请日：2007-02-13
申请人： Cecile Aulnette , Christophe Figuet , Nicolas Daval
发明人： Cecile Aulnette , Christophe Figuet , Nicolas Daval
IPC分类号： H01L21/00
CPC分类号： H01L21/76254 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262
摘要： A method for manufacturing a semiconductor heterostructure by first manufacturing a donor wafer having a first substrate with a first in-plane lattice parameter, a spatially graded buffer layer having a second in-plane lattice parameter, and a strained smoothing layer of a semiconductor material having a third in-plane lattice parameter which has a value between that of the first and second lattice parameters. A top layer is formed on the ungraded layer a top layer of a semiconductor material having a top surface, optionally with a superficial layer present on the top surface and having a thickness that is equal to or smaller than 10 nanometers. Next, a handle wafer of a second substrate having an insulator layer thereon is bonded with the donor wafer in such way that (a) the insulator layer of the handle wafer is bonded directly onto the top surface of the top layer of the donor wafer, or (b) the insulator layer of the handle wafer is bonded onto the superficial layer.
摘要翻译：一种半导体异质结构的制造方法，首先制造具有第一面内晶格参数的第一衬底的施主晶片，具有第二面内晶格参数的空间渐变缓冲层，以及半导体材料的应变平滑化层，具有第一和第二格子参数之间的值的第三平面晶格参数。顶层在未分级层上形成具有顶表面的半导体材料的顶层，任选具有位于顶表面上的表层，并具有等于或小于10纳米的厚度。接下来，其上具有绝缘体层的第二衬底的处理晶片与施主晶片接合，使得（a）把手晶片的绝缘体层直接接合到施主晶片顶层的顶表面上，或者（b）把手晶片的绝缘体层结合到表面层上。

5. 发明授权

US07232737B2 Treatment of a removed layer of silicon-germanium 失效
标题翻译：处理去除的硅 - 锗层
公开(公告)号：US07232737B2
公开(公告)日：2007-06-19
申请号：US11145482
申请日：2005-06-02
申请人： Nicolas Daval
发明人： Nicolas Daval
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/76254 , H01L21/26506 , H01L21/324 , Y10S438/933
摘要： A method of forming a structure that includes a removed layer taken from a donor wafer donor wafer that includes a first layer of Si1-xGex and a second layer of Si1-yGey. The method includes implanting atomic species into the donor wafer to form a zone of weakness in the first layer; bonding the donor wafer to a receiver wafer; detaching the second layer and a portion of the first layer from the donor wafer by supplying energy sufficient to cause cleavage and form an intermediate structure thereof conducting a rapid thermal anneal of the intermediate structure at a temperature of about 1000° C. or more for less than 5 minutes; and removing by selective etching any remaining portions of the first layer of the intermediate structure to provide a semiconductor structure that has the second layer on the receiving wafer.
摘要翻译：一种形成包括从施主晶片施主晶片取出的去除层的结构的方法，所述施主晶片施主晶片包括第一层Si 1-x Ge x x和第二层Si ＆lt; 1-y＆gt; Ge＆gt; y＆lt; /＆gt; 该方法包括将原子物质植入施主晶片中以形成第一层中的弱点区域; 将施主晶片接合到接收器晶片; 通过提供足以引起切割的能量将第二层和第一层的一部分从施主晶片分离，并形成其中间结构，其在约1000℃或更高的温度下进行中间结构的快速热退火以减少超过5分钟; 以及通过选择性蚀刻去除中间结构的第一层的任何剩余部分，以提供在接收晶片上具有第二层的半导体结构。

6. 发明申请

US20120228689A1 WAFER WITH INTRINSIC SEMICONDUCTOR LAYER 有权
标题翻译：带内置半导体层的波形
公开(公告)号：US20120228689A1
公开(公告)日：2012-09-13
申请号：US13416739
申请日：2012-03-09
申请人： Nicolas Daval , Cécile Aulnette , Bich-Yen Nguyen
发明人： Nicolas Daval , Cécile Aulnette , Bich-Yen Nguyen
IPC分类号： H01L27/108 , H01L21/02 , H01L29/16 , H01L21/762
CPC分类号： H01L27/10894 , H01L21/76254 , H01L21/84 , H01L27/10861 , H01L27/1203 , H01L27/1207 , H01L29/66181
摘要： The present invention relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The invention also relates to the wafer that is produced by the new method.
摘要翻译：本发明涉及通过在半导体衬底上设置掺杂层来制造晶片的方法; 在所述掺杂层上提供第一半导体层; 在所述第一半导体层上提供掩埋氧化物层; 以及在所述掩埋氧化物层上提供第二半导体层以形成具有掩埋氧化物层和所述掩埋氧化物层下方的掺杂层的晶片。本发明还涉及通过新方法生产的晶片。

7. 发明授权

US07459374B2 Method of manufacturing a semiconductor heterostructure 有权
标题翻译：半导体异质结构的制造方法
公开(公告)号：US07459374B2
公开(公告)日：2008-12-02
申请号：US11674392
申请日：2007-02-13
申请人： Cécile Aulnette , Christophe Figuet , Nicolas Daval
发明人： Cécile Aulnette , Christophe Figuet , Nicolas Daval
IPC分类号： H01L21/00 , H01L21/302
CPC分类号： H01L21/76254 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262
摘要： A method for manufacturing a semiconductor heterostructure by first manufacturing a donor wafer having a first substrate with a first in-plane lattice parameter, a spatially graded buffer layer having a second in-plane lattice parameter, and a strained smoothing layer of a semiconductor material having a third in-plane lattice parameter which has a value between that of the first and second lattice parameters. A top layer is formed on the ungraded layer a top layer of a semiconductor material having a top surface, optionally with a superficial layer present on the top surface and having a thickness that is equal to or smaller than 10 nanometers. Next, a handle wafer of a second substrate having an insulator layer thereon is bonded with the donor wafer in such way that (a) the insulator layer of the handle wafer is bonded directly onto the top surface of the top layer of the donor wafer, or (b) the insulator layer of the handle wafer is bonded onto the superficial layer.
摘要翻译：一种半导体异质结构的制造方法，首先制造具有第一面内晶格参数的第一衬底的施主晶片，具有第二面内晶格参数的空间渐变缓冲层，以及半导体材料的应变平滑化层，具有第一和第二格子参数之间的值的第三平面晶格参数。顶层在未分级层上形成具有顶表面的半导体材料的顶层，任选具有位于顶表面上的表层，并具有等于或小于10纳米的厚度。接下来，其上具有绝缘体层的第二衬底的处理晶片与施主晶片接合，使得（a）把手晶片的绝缘体层直接接合到施主晶片顶层的顶表面上，或者（b）把手晶片的绝缘体层结合到表面层上。

8. 发明授权

US07452792B2 Relaxation of layers 有权
标题翻译：层层松弛
公开(公告)号：US07452792B2
公开(公告)日：2008-11-18
申请号：US11337267
申请日：2006-01-19
申请人： Nicolas Daval , Zohra Chahra , Romain Larderet
发明人： Nicolas Daval , Zohra Chahra , Romain Larderet
IPC分类号： H01L21/20 , C30B1/02 , C30B1/10
CPC分类号： C30B33/00 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02513 , H01L21/02532 , H01L21/76254
摘要： The invention relates to a method of forming a layer of elastically unstrained crystalline material intended for electronics, optics, or optronics applications, wherein the method is carried out using a structure that includes a first crystalline layer which is elastically strained under tension (or respectively in compression) and a second crystalline layer which is elastically strained in compression (or respectively under tension), with the second layer being adjacent to the first layer. The method includes a step of diffusion between the two layers so that the differences between the respective compositions of the two layers is progressively reduced until they are substantially the same, so that the two layers then form just a single final layer of crystalline material having a composition which, in aggregate, is uniform, and wherein the respective compositions, thicknesses, and degrees of strain of the two layers are initially selected so that, after diffusion, the material then constituting the final layer no longer, in aggregate, exhibits elastic strain. The diffusion can be accomplished by heat treating the structure.
摘要翻译：本发明涉及一种形成用于电子，光学或光电应用的弹性未应变结晶材料层的方法，其中该方法使用包括在张力下弹性应变的第一结晶层（或分别在压缩）和在压缩（或分别在张力下）弹性应变的第二结晶层，其中第二层与第一层相邻。该方法包括在两层之间扩散的步骤，使得两层的各组成之间的差异逐渐减小，直到它们基本相同，使得两层然后仅形成单一最终的结晶材料层，其具有组合物，其总体上是均匀的，并且其中最初选择两层的各自组成，厚度和应变程度，使得在扩散之后，不再集中构成最终层的材料不再具有弹性应变。扩散可以通过热处理结构来实现。

9. 发明授权

US07449394B2 Atomic implantation and thermal treatment of a semiconductor layer 有权
标题翻译：半导体层的原子注入和热处理
公开(公告)号：US07449394B2
公开(公告)日：2008-11-11
申请号：US11179713
申请日：2005-07-11
申请人： Takeshi Akatsu , Nicolas Daval , Nguyet-Phuong Nguyen , Olivier Rayssac , Konstantin Bourdelle
发明人： Takeshi Akatsu , Nicolas Daval , Nguyet-Phuong Nguyen , Olivier Rayssac , Konstantin Bourdelle
IPC分类号： H01L21/46
CPC分类号： H01L21/76254
摘要： Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface; coimplanting two different atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer; bonding the free surface of the second layer to a host wafer; and supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer. Advantageously, the donor wafer includes a SiGe layer, and the co-implantation of atomic species is conducted according to implantation parameters adapted to enable a first species to form the zone of weakness in the SiGe layer, and to enable a second species to provide a concentration peak located beneath the zone of weakness in the donor wafer to thus minimize surface roughness resulting from detachment at the zone of weakness.
摘要翻译：描述形成半导体结构的方法。在一个实施例中，该技术包括提供在第一层上具有第一半导体层和第二半导体层并具有自由表面的施主晶片; 通过第二层的自由表面共同植入两种不同的原子物质，以形成第一层中的弱区; 将第二层的自由表面粘合到主晶片; 并且在弱化区域提供能量以分散包含主晶片，第二层和第一层的一部分的半导体结构。有利地，施主晶片包括SiGe层，并且根据适于使第一种类形成SiGe层中的弱点区域的植入参数来进行原子物质的共同注入，并且使得第二物质能够提供浓度峰位于供体晶片中的弱点之下，从而使得在弱化区分离导致的表面粗糙度最小化。

10. 发明授权

US07276428B2 Methods for forming a semiconductor structure 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07276428B2
公开(公告)日：2007-10-02
申请号：US11059122
申请日：2005-02-16
申请人： Nicolas Daval , Takeshi Akatsu , Nguyet-Phuong Nguyen , Olivier Rayssac
发明人： Nicolas Daval , Takeshi Akatsu , Nguyet-Phuong Nguyen , Olivier Rayssac
IPC分类号： H01L21/46 , H01L21/76
CPC分类号： H01L21/76254
摘要： Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface, implanting atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer, and bonding the free surface of the second layer to a host wafer. The method also includes supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer, conducting a bond strengthening step on the structure after detachment at a temperature of less than about 800° C. to improve the strength of the bond between the second layer and the host wafer, and selectively etching the first layer portion to remove it from the structure and to expose a surface of the second layer. The implanting step includes implantation parameters chosen to minimize surface roughness resulting from detachment at the zone of weakness.
摘要翻译：描述形成半导体结构的方法。在一个实施例中，该技术包括提供在第一层上具有第一半导体层和第二半导体层的施主晶片，并且具有自由表面，通过第二层的自由表面注入原子物质以形成弱区的区域第一层，并将第二层的自由表面结合到主晶片。该方法还包括提供能量以在弱化区域分离包括主晶片，第二层和第一层的一部分的半导体结构，在小于约800℃的温度下分离后在结构上进行结合强化步骤以提高第二层和主晶片之间的结合强度，并且选择性地蚀刻第一层部分以将其从结构上除去并暴露第二层的表面。植入步骤包括选择的植入参数以最小化由于在弱化区域脱离而导致的表面粗糙度。

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