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1. 发明申请

US20070051875A1 OPTOELECTRONIC MEMORY DEVICES 失效
标题翻译：光电存储器件
公开(公告)号：US20070051875A1
公开(公告)日：2007-03-08
申请号：US11161941
申请日：2005-08-23
申请人： Fen Chen , Richard Kontra , Tom Lee , Theodore Levin , Christopher Muzzy , Timothy Sullivan
发明人： Fen Chen , Richard Kontra , Tom Lee , Theodore Levin , Christopher Muzzy , Timothy Sullivan
IPC分类号： H01J40/14 , H01L31/00
CPC分类号： G11C13/0009 , G11C13/0004 , G11C13/004 , G11C13/04 , G11C13/047 , G11C2013/0054 , H01L45/1213 , H01L45/145
摘要： A structure and a method for operating the same. The method comprises providing a resistive/reflective region on a substrate, wherein the resistive/reflective region comprises a material having a characteristic of changing the material's reflectance due to the material absorbing heat; sending an electric current through the resistive/reflective region so as to cause a reflectance change in the resistive/reflective region from a first reflectance value to a second reflectance value different from the first reflectance value; and optically reading the reflectance change in the resistive/reflective region.
摘要翻译：一种结构及其操作方法。该方法包括在衬底上提供电阻/反射区域，其中电阻/反射区域包括具有由于材料吸收热而改变材料的反射率的特性的材料; 发送电流通过电阻/反射区域，以使电阻/反射区域的反射率变化从第一反射率值到不同于第一反射率值的第二反射率值; 并且光学地读取电阻/反射区域中的反射率变化。

2. 发明申请

US20060163685A1 THERMO-MECHANICAL CLEAVABLE STRUCTURE 有权
标题翻译：热机械可靠结构
公开(公告)号：US20060163685A1
公开(公告)日：2006-07-27
申请号：US10905905
申请日：2005-01-26
申请人： Fen Chen , Cathryn Christiansen , Richard Kontra , Tom Lee , Alvin Strong , Timothy Sullivan , Joseph Therrien
发明人： Fen Chen , Cathryn Christiansen , Richard Kontra , Tom Lee , Alvin Strong , Timothy Sullivan , Joseph Therrien
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.
摘要翻译：提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。热机械应力还由于由其产生的气体引起的相变而收缩。当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

3. 发明申请

US20060267144A1 Trench type buried on-chip precision programmable resistor 有权
公开(公告)号：US20060267144A1
公开(公告)日：2006-11-30
申请号：US11481514
申请日：2006-07-06
申请人： John Aitken , Fen Chen , Timothy Sullivan
发明人： John Aitken , Fen Chen , Timothy Sullivan
IPC分类号： H01L29/00
CPC分类号： H01L28/20 , H01L27/101
摘要： An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.

4. 发明申请

US20050263850A1 TRENCH TYPE BURIED ON-CHIP PRECISION PROGRAMMABLE RESISTOR 失效
标题翻译： TRENCH型抛光芯片精密可编程电阻器
公开(公告)号：US20050263850A1
公开(公告)日：2005-12-01
申请号：US10709727
申请日：2004-05-25
申请人： John Aitken , Fen Chen , Timothy Sullivan
发明人： John Aitken , Fen Chen , Timothy Sullivan
IPC分类号： H01L21/20 , H01L27/10 , H01L29/00
CPC分类号： H01L28/20 , H01L27/101
摘要： An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.
摘要翻译：一种片上超小型可编程半导体电阻器件及器件结构及其制造方法。每个半导体电阻器件结构由表现出精确电阻值的一个或多个导电连接的埋沟槽型电阻器元件形成。至少两个半导体电阻器件结构可以通过一个或多个保险丝器件的中间串联或并联配置连接，该熔丝器件可以被吹制以实现期望的总电阻值。

5. 发明申请

US20070130551A1 NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME 有权
标题翻译：深层次微电解法半导体集成电路中导电线路的微结构和界面粗糙度的非破坏性评估
公开(公告)号：US20070130551A1
公开(公告)日：2007-06-07
申请号：US11673369
申请日：2007-02-09
申请人： Fen Chen , Jeffrey Gambino , Jason Gill , Baozhen Li , Timothy Sullivan
发明人： Fen Chen , Jeffrey Gambino , Jason Gill , Baozhen Li , Timothy Sullivan
IPC分类号： G06F17/50
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.
摘要翻译：用于评估半导体集成电路中的线路的新型结构和方法。在每个包括多个线段的晶片上形成第一组多条线。所有线段长度相同。测量线路段的电阻。然后，基于所有部分的电阻来确定第一行几何调整。第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。相同长度和厚度的第二组多条线可以形成在同一晶片上。然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

6. 发明申请

US20060071676A1 NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME 有权
标题翻译：深层次微电解法半导体集成电路中导电线路的微结构和界面粗糙度的非破坏性评估
公开(公告)号：US20060071676A1
公开(公告)日：2006-04-06
申请号：US10711418
申请日：2004-09-17
申请人： Fen Chen , Jeffrey Gambino , Jason Gill , Baozhen Li , Timothy Sullivan
发明人： Fen Chen , Jeffrey Gambino , Jason Gill , Baozhen Li , Timothy Sullivan
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines can be formed on a wafer each of which comprises multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections of all the lines. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments can be determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.
摘要翻译：用于评估半导体集成电路中的线路的新型结构和方法。可以在每个包括多个线段的晶片上形成第一组多条线。所有线段长度相同。测量线路段的电阻。然后，基于所有线的所有部分的电阻来确定第一线几何形状调整。第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。相同长度和厚度的第二组多条线可以形成在同一晶片上。然后，可以基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

7. 发明申请

US20080061902A1 METHOD AND APPARATUS FOR IMPEDANCE MATCHING IN TRANSMISSION CIRCUITS USING TANTALUM NITRIDE RESISTOR DEVICES 有权
公开(公告)号：US20080061902A1
公开(公告)日：2008-03-13
申请号：US11942396
申请日：2007-11-19
申请人： Fen Chen , Kai Feng , Robert Gautheir , Tom Lee
发明人： Fen Chen , Kai Feng , Robert Gautheir , Tom Lee
IPC分类号： H03H7/38
CPC分类号： H03K19/018571
摘要： A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.

8. 发明授权

US08917104B2 Analyzing EM performance during IC manufacturing 有权
标题翻译：分析IC制造过程中的EM性能
公开(公告)号：US08917104B2
公开(公告)日：2014-12-23
申请号：US13222306
申请日：2011-08-31
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/3187 , G01R31/28
CPC分类号： G01R31/2858
摘要： A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.
摘要翻译：用于监测电迁移（EM）性能的测试结构，系统和方法。描述了包括测试结构阵列的系统，其中每个测试结构包括：具有四点电阻测量的EM电阻器，其中第一和第二端子提供电流输入，第三和第四端子提供电压测量; 耦合到所述EM电阻器的第一端子以提供测试电流的第一晶体管; 由一对开关晶体管获得的电压测量，其栅极由选择开关控制，并且其漏极用于在第三和第四端子处提供电压测量。还包括用于选择性地激活测试结构阵列之一的选择开关的解码器; 以及用于输出所选择的测试结构的电压测量的一对输出。

9. 发明授权

US08754655B2 Test structure, method and circuit for simultaneously testing time dependent dielectric breakdown and electromigration or stress migration 失效
标题翻译：测试结构，方法和电路，用于同时测试时间依赖介电击穿和电迁移或应力迁移
公开(公告)号：US08754655B2
公开(公告)日：2014-06-17
申请号：US13207485
申请日：2011-08-11
申请人： David G. Brochu, Jr. , Fen Chen , Roger A. Dufresne , Travis S. Merrill , Michael A. Shinosky
发明人： David G. Brochu, Jr. , Fen Chen , Roger A. Dufresne , Travis S. Merrill , Michael A. Shinosky
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.
摘要翻译：用于同时测试电迁移或应力迁移的测试结构在集成电路中的时间依赖介质击穿失效，使用布置为桥接平衡电路的四个测试结构的测试电路和使用测试电路的测试方法。测试结构的电迁移或应力迁移部分包括通过导电通孔串联连接的导线段的通孔链，形成在集成电路的至少两个相邻布线层中的线段。测试结构的时间依赖介质击穿部分包括在与数字化的线结构相同的布线级别中与所述线段的少于整个部分相邻的所述至少两个相邻布线层之一中的数字化线结构。

10. 发明授权

US08470379B2 Use of a potent product extracted from rhizomes of zingiber officinale in treating a disease associated with Helicobacter pylori 有权
标题翻译：使用从姜黄根茎提取的有效产品治疗与幽门螺杆菌相关的疾病
公开(公告)号：US08470379B2
公开(公告)日：2013-06-25
申请号：US12911143
申请日：2010-10-25
申请人： Feng-Nien Ko , Mo-Chi Cheng , Cheng-Ko Liu , Jen-Wei Chen , Fen Chen , Chao-Chi Yei
发明人： Feng-Nien Ko , Mo-Chi Cheng , Cheng-Ko Liu , Jen-Wei Chen , Fen Chen , Chao-Chi Yei
IPC分类号： A61K36/9068
CPC分类号： A61K36/9068
摘要： A new use of a potent product extracted from rhizomes of Zingiber officinale in treating a disease associated with Helicobacter pylori such as gastritis, gastric ulcer or duodenal ulcer in a patient. The potent product is prepared by a process including the steps of a) preparing a crude extract from rhizomes of Zingiber officinale, said crude extract comprising 6-gingerol and 6-shogaol; b) introducing the crude extract to a normal phase chromatography column, and eluting the column with a first eluent having a polarity lower than that of a mixture of n-hexane and ethyl acetate in a weight ratio of 6:4 to obtain a potent fraction. Preferably, the potent fraction is substantially free of both 6-gingerol and 6-shogaol.
摘要翻译：从姜黄根茎提取的有效产品的新用途，用于治疗与幽门螺杆菌相关的疾病，如胃炎，胃溃疡或十二指肠溃疡。所述有效产物通过以下步骤制备，所述方法包括以下步骤：a）从姜黄根茎制备粗提取物，所述粗提物包含6-姜醇和6-shogaol; b）将粗提取物引入正相色谱柱，并用具有极性低于正己烷和乙酸乙酯的混合物的第一洗脱液以6:4的重量比洗脱柱，以获得有效分数。优选地，有效部分基本上不含6-姜醇和6-硫醇。

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