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1. 发明申请

US20130049793A1 ANALYZING EM PERFORMANCE DURING IC MANUFACTURING 有权
标题翻译：在IC制造过程中分析EM性能
公开(公告)号：US20130049793A1
公开(公告)日：2013-02-28
申请号：US13222306
申请日：2011-08-31
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G01R31/2858
摘要： A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.
摘要翻译：用于监测电迁移（EM）性能的测试结构，系统和方法。描述了包括测试结构阵列的系统，其中每个测试结构包括：具有四点电阻测量的EM电阻器，其中第一和第二端子提供电流输入，第三和第四端子提供电压测量; 耦合到所述EM电阻器的第一端子以提供测试电流的第一晶体管; 由一对开关晶体管获得的电压测量，其栅极由选择开关控制，并且其漏极用于在第三和第四端子处提供电压测量。还包括用于选择性地激活测试结构阵列之一的选择开关的解码器; 以及用于输出所选择的测试结构的电压测量的一对输出。

2. 发明申请

US20120187974A1 Dual Stage Voltage Ramp Stress Test for Gate Dielectrics 审中-公开
标题翻译：栅极电介质的双级电压斜坡应力测试
公开(公告)号：US20120187974A1
公开(公告)日：2012-07-26
申请号：US13010081
申请日：2011-01-20
申请人： David G. Brochu, JR. , Roger A. Dufresne , Charles B. LaRow , Travis S. Merrill , Nilufa Rahim , Ernest Y. Wu
发明人： David G. Brochu, JR. , Roger A. Dufresne , Charles B. LaRow , Travis S. Merrill , Nilufa Rahim , Ernest Y. Wu
IPC分类号： G01R31/26
CPC分类号： G01R31/2623
摘要： A testing system for testing the integrity of a gate dielectric includes a testing apparatus, the testing apparatus including a test probe configured to contact and provide a voltage across the gate dielectric and to measure a current passing through the gate dielectric. The testing system also includes a computing device coupled to the testing apparatus an causing the testing apparatus to apply a constant voltage as part of a first test to the gate dielectric through the test probe until a first predetermined current is measured passing through the gate dielectric and to apply an increasing voltage to the gate dielectric after the first predetermined current is measured.
摘要翻译：用于测试栅极电介质的完整性的测试系统包括测试装置，测试装置包括被配置成接触并提供横跨栅极电介质的电压并测量通过栅极电介质的电流的测试探针。测试系统还包括耦合到测试装置的计算设备，使得测试设备通过测试探针将恒定电压作为第一测试的一部分施加到栅极电介质，直到通过栅极电介质测量第一预定电流，并且在测量第一预定电流之后，向栅极电介质施加增加的电压。

3. 发明授权

US09029172B2 On-chip poly-to-contact process monitoring and reliability evaluation system and method of use 有权
标题翻译：片上多点接触过程监控与可靠性评估系统及使用方法
公开(公告)号：US09029172B2
公开(公告)日：2015-05-12
申请号：US13354547
申请日：2012-01-20
申请人： Fen Chen , Roger A. Dufresne , Timothy D. Sullivan , Yanfeng Wang
发明人： Fen Chen , Roger A. Dufresne , Timothy D. Sullivan , Yanfeng Wang
IPC分类号： H01L21/00 , H01L21/66
CPC分类号： H01L22/34 , H01L22/12 , H01L2924/00 , H01L2924/0002
摘要： An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage.
摘要翻译：提供片上多点接触式过程监测和可靠性评估系统及其使用方法。一种方法包括确定与相应的一个或多个原始半导体结构相对应的一个或多个浅沟槽隔离（STI）测量结构中的每一个的击穿电场。该方法还包括确定与相应的一个或多个原始半导体结构相对应的一个或多个衬底测量结构中的每一个的击穿电压。该方法还包括基于所确定的击穿电场和所确定的击穿电压，确定一个或多个原始半导体结构中的每一个的栅极和触点之间的空间。

4. 发明申请

US20130191047A1 ON-CHIP POLY-TO-CONTACT PROCESS MONITORING AND RELIABILITY EVALUATION SYSTEM AND METHOD OF USE 有权
标题翻译：片上多点接触过程监测与可靠性评估系统及其使用方法
公开(公告)号：US20130191047A1
公开(公告)日：2013-07-25
申请号：US13354547
申请日：2012-01-20
申请人： Fen CHEN , Roger A. DUFRESNE , Timothy D. SULLIVAN , Yanfeng WANG
发明人： Fen CHEN , Roger A. DUFRESNE , Timothy D. SULLIVAN , Yanfeng WANG
IPC分类号： G01R31/26 , G06F19/00
CPC分类号： H01L22/34 , H01L22/12 , H01L2924/00 , H01L2924/0002
摘要： An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage.
摘要翻译：提供片上多点接触式过程监测和可靠性评估系统及其使用方法。一种方法包括确定与相应的一个或多个原始半导体结构相对应的一个或多个浅沟槽隔离（STI）测量结构中的每一个的击穿电场。该方法还包括确定与相应的一个或多个原始半导体结构相对应的一个或多个衬底测量结构中的每一个的击穿电压。该方法还包括基于所确定的击穿电场和所确定的击穿电压来确定一个或多个原始半导体结构中的每一个的栅极和触点之间的空间。

5. 发明申请

US20130038334A1 TEST STRUCTURE, METHOD AND CIRCUIT FOR SIMULTANEOUSLY TESTING TIME DEPENDENT DIELECTRIC BREAKDOWN AND ELECTROMIGRATION OR STRESS MIGRATION 失效
标题翻译：测试结构，方法和电路同时测试时间依赖电介质断开和电力或应力移动
公开(公告)号：US20130038334A1
公开(公告)日：2013-02-14
申请号：US13207485
申请日：2011-08-11
申请人： David G. Brochu, JR. , Fen Chen , Roger A. Dufresne , Travis S. Merrill , Michael A. Shinosky
发明人： David G. Brochu, JR. , Fen Chen , Roger A. Dufresne , Travis S. Merrill , Michael A. Shinosky
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.
摘要翻译：用于同时测试电迁移或应力迁移的测试结构在集成电路中的时间依赖介质击穿失效，使用布置为桥接平衡电路的四个测试结构的测试电路和使用测试电路的测试方法。测试结构的电迁移或应力迁移部分包括通过导电通孔串联连接的导线段的通孔链，形成在集成电路的至少两个相邻布线层中的线段。测试结构的时间依赖介质击穿部分包括在与数字化的线结构相同的布线级别中与所述线段的少于整个部分相邻的所述至少两个相邻布线层之一中的数字化线结构。

6. 发明授权

US08917104B2 Analyzing EM performance during IC manufacturing 有权
标题翻译：分析IC制造过程中的EM性能
公开(公告)号：US08917104B2
公开(公告)日：2014-12-23
申请号：US13222306
申请日：2011-08-31
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/3187 , G01R31/28
CPC分类号： G01R31/2858
摘要： A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.
摘要翻译：用于监测电迁移（EM）性能的测试结构，系统和方法。描述了包括测试结构阵列的系统，其中每个测试结构包括：具有四点电阻测量的EM电阻器，其中第一和第二端子提供电流输入，第三和第四端子提供电压测量; 耦合到所述EM电阻器的第一端子以提供测试电流的第一晶体管; 由一对开关晶体管获得的电压测量，其栅极由选择开关控制，并且其漏极用于在第三和第四端子处提供电压测量。还包括用于选择性地激活测试结构阵列之一的选择开关的解码器; 以及用于输出所选择的测试结构的电压测量的一对输出。

7. 发明授权

US08754655B2 Test structure, method and circuit for simultaneously testing time dependent dielectric breakdown and electromigration or stress migration 失效
标题翻译：测试结构，方法和电路，用于同时测试时间依赖介电击穿和电迁移或应力迁移
公开(公告)号：US08754655B2
公开(公告)日：2014-06-17
申请号：US13207485
申请日：2011-08-11
申请人： David G. Brochu, Jr. , Fen Chen , Roger A. Dufresne , Travis S. Merrill , Michael A. Shinosky
发明人： David G. Brochu, Jr. , Fen Chen , Roger A. Dufresne , Travis S. Merrill , Michael A. Shinosky
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.
摘要翻译：用于同时测试电迁移或应力迁移的测试结构在集成电路中的时间依赖介质击穿失效，使用布置为桥接平衡电路的四个测试结构的测试电路和使用测试电路的测试方法。测试结构的电迁移或应力迁移部分包括通过导电通孔串联连接的导线段的通孔链，形成在集成电路的至少两个相邻布线层中的线段。测试结构的时间依赖介质击穿部分包括在与数字化的线结构相同的布线级别中与所述线段的少于整个部分相邻的所述至少两个相邻布线层之一中的数字化线结构。

8. 发明申请

US20130106452A1 REAL-TIME ON-CHIP EM PERFORMANCE MONITORING 有权
标题翻译：实时片上EM性能监控
公开(公告)号：US20130106452A1
公开(公告)日：2013-05-02
申请号：US13282090
申请日：2011-10-26
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/3187
CPC分类号： G01R31/3004
摘要： An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.
摘要翻译：用于监测电迁移（EM）性能的集成电路，测试结构和方法。描述了一种包括用于测量片上电迁移（EM）性能的方法的方法，包括：提供用应力电流连续供电的第一片上传感器; 提供仅在具有额定电流的测量周期期间供电的第二片上传感器; 在一系列测量周期中的每一个期间，从第一片上传感器获得第一电阻测量值和来自第二片上传感器的第二电阻测量值; 并处理第一和第二电阻测量。

9. 发明授权

US08890556B2 Real-time on-chip EM performance monitoring 有权
标题翻译：实时片上EM性能监控
公开(公告)号：US08890556B2
公开(公告)日：2014-11-18
申请号：US13282090
申请日：2011-10-26
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/3187 , G01R31/30
CPC分类号： G01R31/3004
摘要： An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.
摘要翻译：用于监测电迁移（EM）性能的集成电路，测试结构和方法。描述了一种包括用于测量片上电迁移（EM）性能的方法的方法，包括：提供用应力电流连续供电的第一片上传感器; 提供仅在具有额定电流的测量周期期间供电的第二片上传感器; 在一系列测量周期中的每一个期间，从第一片上传感器获得第一电阻测量值和来自第二片上传感器的第二电阻测量值; 并处理第一和第二电阻测量。

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