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1. 发明申请

US20030082897A1 Method for forming bumps, semiconductor device, and solder paste 有权
公开(公告)号：US20030082897A1
公开(公告)日：2003-05-01
申请号：US10191533
申请日：2002-07-10
申请人： FUJITSU LIMITED
发明人： Seiki Sakuyama , Yasuo Yamagishi , Masataka Mizukoshi
IPC分类号： H01L021/44
CPC分类号： H05K3/3484 , H01L21/4853 , H01L21/6835 , H01L23/49883 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1147 , H01L2224/13099 , H01L2224/141 , H01L2224/16145 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01056 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1532 , H05K3/3436 , H05K3/3452 , H05K2201/0266 , H05K2201/10477 , H05K2201/10674 , H05K2201/10734 , H05K2203/043 , H05K2203/0568 , H05K2203/0574 , H05K2203/0577 , H05K2203/0769
摘要： The present invention relates to a method for forming bumps on a substrate provided with electrode pads. The method includes providing a mask having openings corresponding to the electrode pads, filling each of the openings with a solder paste, and heat treating the solder paste, wherein the solder paste includes solder powder. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is greater than the thickness of the mask and no more than 1.5 times this thickness. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is not less than 40% the diameter of the opening portions, or no less than 30 wt % of particles whose diameter is 40 to 100% the thickness of the mask.

2. 发明申请

US20030200654A1 Method of manufacturing electronic circuit component 有权
标题翻译：制造电子电路元件的方法
公开(公告)号：US20030200654A1
公开(公告)日：2003-10-30
申请号：US10420751
申请日：2003-04-23
申请人： FUJITSU LIMITED
发明人： Koji Omote , Masataka Mizukoshi , Osamu Taniguchi
IPC分类号： H01L021/44 , H01L021/48 , H01L021/50
CPC分类号： H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2225/06541 , H01L2225/06572 , H01L2924/15192 , H01L2924/3011 , Y10T29/49155 , Y10T29/49165
摘要： A method of manufacturing an electronic circuit component, comprises the steps of: (a) forming a first thin film circuit element on a surface of a circuit board made of an Si substrate; (b) forming a hole or trench from the surface of the circuit board through at least a portion of a thickness of the Si substrate by etching; (c) forming an insulating film covering a surface of the formed hole or trench; (d) adhering a dry film of photoresist to the surface of the circuit board, the dry film capping an opening of the hole or trench; (e) patterning the dry film; and (f) by using the patterned dry film as a mask, etching the insulating film. An electronic circuit component having through conductors and being less influenced by high temperature annealing can be manufactured.
摘要翻译：一种制造电子电路部件的方法，包括以下步骤：（a）在由Si衬底制成的电路板的表面上形成第一薄膜电路元件; （b）通过蚀刻从所述电路板的表面通过所述Si衬底的厚度的至少一部分形成孔或沟槽; （c）形成覆盖所形成的孔或沟槽的表面的绝缘膜; （d）将光致抗蚀剂的干膜粘附到电路板的表面，干膜封盖孔或沟槽的开口; （e）图案化干膜; 和（f）通过使用图案化的干膜作为掩模，蚀刻绝缘膜。可以制造具有通过导体并受较低温度退火影响的电子电路部件。

3. 发明申请

US20030148593A1 Electrode connection method, electrode surface activation apparatus, electrode connection apparatus, connection method of electronic components and connected structure 有权
标题翻译：电极连接方法，电极表面激活装置，电极连接装置，电子部件的连接方法和连接结构
公开(公告)号：US20030148593A1
公开(公告)日：2003-08-07
申请号：US10347224
申请日：2003-01-21
申请人： FUJITSU LIMITED
发明人： Keishiro Okamoto , Masataka Mizukoshi , Yasuo Yamagishi
IPC分类号： H01L021/46 , H01L021/44 , H01L021/30 , H01L021/4763
CPC分类号： H05K3/328 , H01L21/563 , H01L24/29 , H01L2224/13109 , H01L2224/13111 , H01L2224/29109 , H01L2224/29111 , H01L2224/2919 , H01L2224/73104 , H01L2224/73203 , H01L2224/83101 , H01L2224/83193 , H01L2924/01005 , H01L2924/01006 , H01L2924/01018 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/1579 , H01L2924/3511 , H05K3/3489 , H01L2924/01083 , H01L2924/00014 , H01L2924/0665
摘要： An electrode connecting method of connecting a first electrode and a second electrode is disclosed. The respective bonding surfaces of the first and second electrodes are activated. Then, each of the first and second electrodes having the activated surfaces is coated with a coating member for maintaining an activated state. A solid state bond between the first electrode and the second electrode is formed by pressure welding the first electrode and the second electrode so that the first and second electrodes break through the coating members.
摘要翻译：公开了一种连接第一电极和第二电极的电极连接方法。第一和第二电极的各自的接合表面被激活。然后，具有活化表面的第一和第二电极中的每一个涂覆有用于保持激活状态的涂层构件。第一电极和第二电极之间的固态键合是通过对第一电极和第二电极进行加压焊接形成的，以使第一和第二电极穿过涂覆部件。

4. 发明申请

US20010011898A1 IC socket, a test method using the same and an IC socket mounting mechanism 有权
标题翻译： IC插座，使用其的测试方法和IC插座安装机构
公开(公告)号：US20010011898A1
公开(公告)日：2001-08-09
申请号：US09809204
申请日：2001-03-16
申请人： Fujitsu Limited
发明人： Makoto Haseyama , Shigeyuki Maruyama , Masataka Mizukoshi , Futoshi Fukaya
IPC分类号： G01R031/02
CPC分类号： G01R1/0466 , G01R1/0483 , G01R1/06738 , G01R31/2863 , G01R31/2886 , H01L2924/00013 , H01L2224/29099
摘要： An IC to be tested having solder bumps is mounted on an IC socket mounted on a test board. The IC socket is provided with a contact unit including a plurality of straight contact pins each having an lower end connected to the test board and an upper end connected to the solder bumps and also including an elastic member for supporting the plurality of contact pins. A diameter of the plurality of contact pins is configured to be sufficiently small for the plurality of contact pins to pierce the respective solder bumps so that an electrical connection is established by the upper end of each of the plurality of solder bumps piercing an associated one of the solder bumps.
摘要翻译：将被测试的具有焊锡凸块的IC安装在安装在测试板上的IC插座上。 IC插座设置有接触单元，该接触单元包括多个直接接触针，每个具有连接到测试板的下端和连接到焊料凸块的上端，并且还包括用于支撑多个接触针的弹性构件。多个接触针的直径被构造成足够小以使多个接触针刺穿相应的焊料凸块，使得通过多个焊料凸块中的每一个的上端穿过相关联的一个焊接凸块来建立电连接焊锡凸块。

5. 发明申请

US20020130164A1 Solder jointing system, solder jointing method, semiconductor device manufacturing method, and semiconductor device manufacturing system 有权
标题翻译：焊接接头系统，焊接方法，半导体器件制造方法以及半导体器件制造系统
公开(公告)号：US20020130164A1
公开(公告)日：2002-09-19
申请号：US09970802
申请日：2001-10-05
申请人： Fujitsu Limited
发明人： Hirohisa Matsuki , Hiroyuki Matsui , Eiji Yoshida , Takao Ohno , Koki Otake , Akiyo Mizutani , Motoshu Miyajima , Masataka Mizukoshi , Eiji Watanabe
IPC分类号： B23K020/08 , B23K001/08 , B23K020/14 , B23K031/02
CPC分类号： B23K1/008 , B23K2101/36 , H05K3/3489
摘要： There are provided a chamber having openings which are opened to an outer air and through which a solder-adhered object w is passed and having a heating/melting area and carrying areas arranged adjacent to the heating/melting area, a carrying mechanism for carrying the solder-adhered object w into the heating/melting area, a formic-acid supplying means for supplying a formic acid into the heating/melting area, an exhausting means for exhausting a gas from the heating/melting area and its neighboring area to lower a pressure in the heating/melting area rather than an outer air, heating means for heating directly or indirectly the solder-adhered object w in the heating/melting area, and air-stream suppressing means for disturbing a gas flow between the heating/melting area and the carrying areas. Accordingly, there can be provided a solder jointing system for jointing solder layers of the semiconductor device, the electronic device, or the like to the wirings or the pads, which is capable of having a high processing ability and preventing re-oxidation.
摘要翻译：设置有具有向外部空气开放的开口的室，通过焊锡物体w通过并具有加热/熔化区域和与加热/熔融区域相邻布置的承载区域的开口，用于承载焊接物体w进入加热/熔化区域，用于向加热/熔化区域供应甲酸的甲酸供给装置，用于从加热/熔化区域及其相邻区域排出气体的排气装置，以降低在加热/熔化区域而不是外部空气中的压力，用于在加热/熔化区域中直接或间接加热焊料附着物体w的加热装置，以及用于扰乱加热/熔化区域之间的气流的空气流抑制装置和携带区域。因此，可以提供一种用于将半导体器件，电子器件等的焊料层接合到布线或焊盘上的焊接接合系统，其能够具有高处理能力并防止再氧化。

6. 发明申请

US20010008310A1 Method for forming bumps, semiconductor device, and solder paste 审中-公开
标题翻译：用于形成凸块，半导体器件和焊膏的方法
公开(公告)号：US20010008310A1
公开(公告)日：2001-07-19
申请号：US09746336
申请日：2001-03-15
申请人： FUJITSU LIMITED
发明人： Seiki Sakuyama , Yasuo Yamagishi , Masataka Mizukoshi
IPC分类号： H01L021/44 , H01L021/48 , H01L021/50 , H01L023/48 , H01L023/52 , H01L029/40
CPC分类号： H05K3/3484 , H01L21/4853 , H01L21/6835 , H01L23/49883 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/11472 , H01L2224/11474 , H01L2224/13099 , H01L2224/141 , H01L2224/16145 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01056 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1532 , H05K3/3436 , H05K3/3452 , H05K2201/0266 , H05K2201/10477 , H05K2201/10674 , H05K2201/10734 , H05K2203/043 , H05K2203/0568 , H05K2203/0574 , H05K2203/0577 , H05K2203/0769
摘要： The present invention relates to a bump formation method, comprising the steps of providing a mask, in which a plurality of openings have been formed corresponding to a plurality of electrode pads, to a substrate provided with this plurality of electrode pads, filling the openings with a solder paste, and heat treating the solder paste. The solder paste contains a solder powder. This solder powder is one that contains no more than 10 wt % particles whose diameter is greater than the thickness of the mask and no more than 1.5 times this thickness. Preferably, this solder powder is one that contains no more than 10 wt % particles whose diameter is greater than 40% of the diameter of the openings, or one that contains no more than 30 wt % particles whose diameter is 40 to 100% the thickness of the mask.
摘要翻译：凸点形成方法技术领域本发明涉及一种凸块形成方法，包括以下步骤：将具有多个电极焊盘的多个开口形成的掩模提供给设置有该多个电极焊盘的基板，焊膏，并对焊膏进行热处理。焊膏含有焊料粉末。该焊料粉末是含有不超过10重量％的直径大于掩模厚度且不大于该厚度的1.5倍的颗粒。优选地，该焊料粉末是含有不超过10重量％的直径大于开口直径的40％的颗粒，或者包含不超过30重量％的直径为40至100重量％的颗粒的焊料粉末的面具。

7. 发明申请

US20040009666A1 Thin film multi-layer wiring substrate and method for manufacturing same 有权
标题翻译：薄膜多层布线基板及其制造方法
公开(公告)号：US20040009666A1
公开(公告)日：2004-01-15
申请号：US10338646
申请日：2003-01-09
申请人： FUJITSU LIMITED
发明人： Yoshikatsu Ishizuki , Nobuyuki Hayashi , Masataka Mizukoshi , Yasuo Yamagishi
IPC分类号： H01L021/302 , H01L021/461
CPC分类号： H05K1/0221 , H01L2223/6622 , H05K3/4647 , H05K3/467 , H05K2201/09809 , H05K2203/0733 , Y10T428/24917 , Y10T428/24926
摘要： A thin film multi-layer wiring substrate comprising a plurality of wiring layers, each adjacent pair of wiring layers being separated by an insulating layer, wherein at least one of the wiring layers includes wiring formed by an inner conductor member and a conductor layer surrounding the periphery thereof through an insulating material. A printed circuit board comprising a signal line conductor formed on a first insulating layer which selectively covers a first ground layer spreading on a substrate, shield walls extending across gaps on both sides of the signal line conductor, and conductively connected to the first ground layer, and a second ground layer conductively connected to the shield walls, stretching across gaps above the signal line conductor, and in which a plurality of openings having lengths and distances of equal to or less than one quarter of a frequency handled by the signal line conductor are formed, is also disclosed.
摘要翻译：一种薄膜多层布线基板，包括多个布线层，每个相邻的一对布线层被绝缘层隔开，其中至少一个布线层包括由内部导体构件形成的布线和围绕该布线层的导体层其周边通过绝缘材料。一种印刷电路板，包括形成在第一绝缘层上的信号线导体，其选择性地覆盖在基板上扩展的第一接地层，跨过信号线导体两侧的间隙延伸的屏蔽壁，并且导电连接到第一接地层，以及导电连接到屏蔽壁的第二接地层，跨越信号线导体上方的间隙延伸，并且其中具有等于或小于由信号线导体处理的频率的四分之一的长度和距离的多个开口是形成，也被披露。

8. 发明申请

US20030173678A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20030173678A1
公开(公告)日：2003-09-18
申请号：US10366609
申请日：2003-02-14
申请人： Fujitsu Limited
发明人： Masataka Mizukoshi
IPC分类号： H01L023/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/10 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05025 , H01L2224/05027 , H01L2224/0508 , H01L2224/0557 , H01L2224/05572 , H01L2224/05573 , H01L2224/13 , H01L2224/13025 , H01L2224/13099 , H01L2225/06513 , H01L2225/06541 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00
摘要： The semiconductor device comprises: a substrate 10 having a through-hole 18 formed therethrough; an electrode 12 formed on one surface of the substrate 10, through-electrode 38 formed in the through-hole 18 and electrically connected to the electrode 12. The through-electrode 38 includes conducting films 26, 32 formed along the inside wall of the through-hole 18, and pin-shaped projection 36 formed on the conducting film exposed on the other surface of the substrate 10. Whereby the pin-shaped projection absorbs stress generated in mounting the semiconductor device, and stable connection can be realized. The pin-shaped projection can be easily formed by plating. A length of the pin-shaped projection can be freely controlled. Accordingly, the through-electrode having the pin-shaped projection can be stably formed without restrictions of shapes and lengths of the hole formed in a substrate.
摘要翻译：半导体器件包括：具有穿过其形成的通孔18的衬底10; 形成在基板10的一个表面上的电极12，形成在通孔18中并与电极12电连接的通孔38.贯通电极38包括沿着贯通孔18的内壁形成的导电膜26,32 孔18和形成在导电膜上的销状突起36暴露在基板10的另一个表面上。由此，销状突起吸收在安装半导体器件时产生的应力，并且可以实现稳定的连接。可以通过电镀容易地形成销状突起。可以自由地控制销状突起的长度。因此，可以稳定地形成具有销状突起的贯通电极，而不会限制形成在基板中的孔的形状和长度。

9. 发明申请

US20030129814A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20030129814A1
公开(公告)日：2003-07-10
申请号：US10329515
申请日：2002-12-27
申请人： FUJITSU LIMITED
发明人： Masataka Mizukoshi
IPC分类号： H01L021/20
CPC分类号： H01L21/76898 , B23K26/146 , B23K26/382 , B23K26/389 , B23K26/40 , B23K2101/40 , B23K2103/50 , H01L2224/02381 , H01L2224/05001 , H01L2224/05009 , H01L2224/05025 , H01L2224/05027 , H01L2224/0508 , H01L2224/05556 , H01L2224/0557 , H01L2224/05572 , H01L2224/13025 , H01L2224/16145 , Y10S438/963
摘要： According to the present invention, of the resist film applied to the entire surface of the silicon substrate, the part on the electrode pattern is removed and an opening shaped like a dish in which the diameter of the upper part is larger than that of the lower part is formed, wherein the diameter of the lower part is smaller than the outer diameter of the electrode pattern. The electrode pattern exposed at the bottom of the opening is removed by the etching process. Next, the silicon substrate is tilted and a laser beam is irradiated toward the silicon substrate exposed at the bottom of the opening with water running over the surface of the resist film in air, and a hole is formed.
摘要翻译：根据本发明，在硅基片的整个表面上施加的抗蚀剂膜，除去电极图案上的部分和上部的直径大于下部的直径的碟状的开口形成部分，其中下部的直径小于电极图案的外径。通过蚀刻工艺去除在开口底部暴露的电极图案。接下来，硅衬底倾斜，并且在空气中在抗蚀剂膜的表面上流动的水，在开口底部暴露的硅衬底照射激光束，并形成孔。

10. 发明申请

US20030124868A1 Pattern forming method 失效
标题翻译：图案形成方法
公开(公告)号：US20030124868A1
公开(公告)日：2003-07-03
申请号：US10320398
申请日：2002-12-17
申请人： FUJITSU LIMITED
发明人： Masataka Mizukoshi
IPC分类号： H01L021/302 , H01L021/461
CPC分类号： G03F9/7003 , G03F7/70291 , G03F7/70466 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/24137 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01078 , H01L2924/04941 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/30107
摘要： A pattern forming method comprising the steps of: detecting a position of a base pattern formed on a substrate; forming a photosensitive resin film on the substrate; correcting a pattern data of a pattern to be formed on the substrate, based on a positional information of the base pattern to thereby compute a corrected pattern data; displaying a mask pattern on a liquid crystal panel, based on the corrected pattern data; and exposing the photosensitive resin film with the liquid crystal panel as a mask and developing the same to thereby pattern the photosensitive resin film. Even when a base pattern has rotations, shrinkages, distortions, etc., a prescribed upper layer pattern can be formed in alignment with the lower layer pattern.
摘要翻译：一种图案形成方法，包括以下步骤：检测形成在基底上的基底图案的位置; 在基板上形成感光性树脂膜; 基于所述基本图案的位置信息来校正要在所述基板上形成的图案的图案数据，从而计算校正图案数据; 基于校正的图案数据在液晶面板上显示掩模图案; 并将作为掩模的液晶面板的感光性树脂膜曝光并使其显影，从而对感光性树脂膜进行图案化。即使当基底图案具有旋转，收缩，变形等时，也可以形成与下层图案对准的规定的上层图案。

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