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1. 发明授权

US07126435B2 Voltage controlled oscillator amplitude control circuit 有权
标题翻译：压控振荡器振幅控制电路
公开(公告)号：US07126435B2
公开(公告)日：2006-10-24
申请号：US10948087
申请日：2004-09-22
申请人： Eric H. Naviasky , Michael A. Casas
发明人： Eric H. Naviasky , Michael A. Casas
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03B5/04 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03B5/1278 , H03L7/099
摘要： A voltage controlled oscillator amplitude control circuit has a voltage controlled oscillator circuit to output an oscillating signal having a controlled amplitude. It also has a control circuit to control the amplitude of the oscillating signal by providing a dominant pole, a filtering function, rectification, and a gain at a single node of the circuit.
摘要翻译：压控振荡器幅度控制电路具有压控振荡器电路，以输出具有受控幅度的振荡信号。它还具有通过在电路的单个节点处提供主极，滤波功能，整流和增益来控制振荡信号的幅度的控制电路。

2. 发明授权

US06608860B1 Low power dissipation, high linearity transmitter 有权
标题翻译：功耗低，线性度高
公开(公告)号：US06608860B1
公开(公告)日：2003-08-19
申请号：US09434592
申请日：1999-11-05
申请人： Eric H. Naviasky , Martin J. Mengele
发明人： Eric H. Naviasky , Martin J. Mengele
IPC分类号： H04L2500
CPC分类号： H04L25/0266
摘要： An improved transmitter capable of achieving high linearity with minimal power dissipation is disclosed, comprising a digital phase splitter and an output stage. The digital phase splitter includes a positive phase digital-to-analog converter (DAC) for converting the positive phase portion of a set of input digital data into an analog signal, and a negative phase DAC for converting the negative phase portion of the set of input digital data into another analog signal. The analog signals from the phase splitter are passed to the output stage for transmission onto a transmission medium. The transmitter may be operated in low power dissipation mode. Because the phases of the input digital signal are split in the digital domain prior to the output stage, the output stage experiences minimal crossover distortion. Consequently, the transmitter is able to minimize power dissipation without suffering from poor linearity performance.
摘要翻译：公开了一种能够以最小功耗实现高线性度的改进的发射机，包括数字分相器和输出级。数字分相器包括用于将一组输入数字数据的正相部分转换为模拟信号的正相数模转换器（DAC），以及用于将该组输出数字数据的负相位部分转换为将数字数据输入到另一个模拟信号。来自分相器的模拟信号被传送到输出级，以便传输到传输介质上。发射机可以在低功耗模式下工作。由于输入数字信号的相位在输出级之前在数字域中分离，所以输出级经历最小的交叉失真。因此，发射机能够最小化功率耗散，而不会受到线性性能的差。

3. 发明授权

US5198815A Two loop superconducting sigma-delta analog-to-digital converters 失效
标题翻译：双回路超导Σ-Δ模数转换器
公开(公告)号：US5198815A
公开(公告)日：1993-03-30
申请号：US807040
申请日：1991-12-12
申请人： John X. Przybysz , Donald L. Miller , Eric H. Naviasky
发明人： John X. Przybysz , Donald L. Miller , Eric H. Naviasky
IPC分类号： H03M3/02
CPC分类号： H03M3/438 , H03M3/43
摘要： A two-loop superconducting sigma-delta analog-to-digital converter includes a first superconducting inductor to which the analog signal is applied. A resistor converts to current in the first inductor to a voltage which is applied to a second superconducting inductor. The current in the second inductor, which increases quadradically with time, is applied to an overdamped Josephson junction which kicks back a single quantum voltage pulse each time its critical current is exceeded. This pulse reduces the current in the second inductor and serves as a digital ONE output. The pulses are also applied to an underdamped Josephson junction in a feedback pulse generator which latches at its gap voltage for the remainder of a half cycle of an ac bias current. This provides a voltage source for the primary of a superconducting transformer having a mutual inductance which produces sufficient flux in the secondary to cause a SQUID to generate in response to each pulse from the quantizer a selected number of feedback pulses which are applied to the first inductor.
摘要翻译：双回路超导Σ-Δ模数转换器包括施加模拟信号的第一超导电感器。电阻器将第一电感器中的电流转换为施加到第二超导电感器的电压。随着时间的推移，第二电感器中的电流逐渐增加，被施加到过阻尼的约瑟夫逊结，每当超过其临界电流时，它将踢回单个量子电压脉冲。该脉冲降低了第二电感器中的电流，并且用作数字ONE输出。脉冲也被施加到反馈脉冲发生器中的欠阻尼约瑟夫逊结，该反馈脉冲发生器在交流偏置电流的剩余半周期内以其间隙电压锁存。这为具有互感的超导变压器的初级电压提供电压源，该互感器在辅助电路中产生足够的通量，以使SQUID响应于来自量化器的每个脉冲而产生选定数量的反馈脉冲，该反馈脉冲施加到第一电感器。

4. 发明授权

US06331833B1 Highly linear sigma-delta modulator having graceful degradation of signal-to-noise ratio in overload condition 有权
标题翻译：高度线性的Σ-Δ调制器在过载条件下具有信噪比的优雅降低
公开(公告)号：US06331833B1
公开(公告)日：2001-12-18
申请号：US09488660
申请日：2000-01-20
申请人： Eric H. Naviasky , Michael M. Hufford , Jeremy Lubkin
发明人： Eric H. Naviasky , Michael M. Hufford , Jeremy Lubkin
IPC分类号： H03M106
CPC分类号： H03M3/366 , H03M3/458
摘要： A multi-bit analog-to-digital converter architecture, which during normal operation behaves like a single-bit converter, thus sharing the high linearity and low distortion properties of the simpler system. When a high input signal is applied, a second bit is triggered and the system behaves like a more complex multi-bit system, providing system stability where a single-bit comparator would overload and the system would become unstable. During normal operation, a single-bit converter is sufficient to stabilize the system. When the input is a large, sustained signal (relative to the full scale of the converter) this single-bit approach is not sufficient to maintain system stability. Thus, if the input to the analog-to-digital converter is close to its maximum or minimum range (implying a large positive or negative input signal) a second bit is triggered, providing stable linearity where the signal-to-noise ratio of a conventional sigma-delta converter would rapidly drop off.
摘要翻译：在正常操作期间，多位模数转换器架构表现得像单位转换器，从而共享更简单系统的高线性度和低失真特性。当施加高输入信号时，触发第二个位，并且系统的行为就像一个更复杂的多位系统，提供系统稳定性，其中单位比较器将过载并且系统变得不稳定。在正常操作期间，单位转换器足以稳定系统。当输入是一个大的持续信号（相对于转换器的满刻度）时，这种单位方式不足以维持系统的稳定性。因此，如果模数转换器的输入接近其最大或最小范围（意味着大的正或负输入信号），则触发第二位，从而提供稳定的线性度，其中信号 - 噪声比为传统的Σ-Δ转换器将迅速下降。

5. 发明授权

US5426416A Automotive current sensor 失效
标题翻译：汽车电流传感器
公开(公告)号：US5426416A
公开(公告)日：1995-06-20
申请号：US963711
申请日：1992-10-19
申请人： Daniel W. Jefferies , Eric H. Naviasky , Donald J. Grone , Joseph G. Henderson
发明人： Daniel W. Jefferies , Eric H. Naviasky , Donald J. Grone , Joseph G. Henderson
IPC分类号： G01R15/14 , G01R31/00 , G08B21/00
CPC分类号： G01R31/006 , G01R19/0092
摘要： A high-amperage current sensor is disclosed which is suitable for use in an automotive electrical system and which is operatively unaffected by changes in ambient temperature. The current sensor utilizes a shunt assembly having at least one low-resistance shunt element connectable in line between a source of electrical energy and a load. Circuitry preferably configured on an application specific integrated circuit measures voltage drop across the shunt element due to current flow. As a result, an output signal is produced which may be fed to external circuitry for further processing. In presently preferred embodiments, the sensor may comprise analog circuitry producing an analog output signal and/or digital circuitry producing a digital output signal.
摘要翻译：公开了一种适用于汽车电气系统的高安培电流传感器，其不受环境温度变化的影响。电流传感器利用分流组件，其具有可连接在电能源和负载之间的至少一个低电阻分流元件。优选地在专用集成电路上配置的电路测量由于电流而跨越分流元件的电压降。结果，产生可以被馈送到外部电路进行进一步处理的输出信号。在目前优选的实施例中，传感器可以包括产生模拟输出信号的模拟电路和/或产生数字输出信号的数字电路。

6. 发明授权

US5140324A Superconducting sigma-delta analog-to-digital converter 失效
标题翻译：超导Σ-Δ模数转换器
公开(公告)号：US5140324A
公开(公告)日：1992-08-18
申请号：US710856
申请日：1991-06-06
申请人： John X. Przybysz , Donald L. Miller , Eric H. Naviasky
发明人： John X. Przybysz , Donald L. Miller , Eric H. Naviasky
IPC分类号： H03M3/02
CPC分类号： H03M3/456 , H03M3/43
摘要： A superconducting sigma-delta analog-to-digital converter utilizes a superconducting inductor as the integrator and a Josephson junction connected in series between the inductor and ground as the quantizer. A SQUID generates sampling pulses at a selected GHz frequency which add to the inductor current flowing through the Josephson junction. When the combined current through the Josephson junction exceeds the critical current of the Josephson junction, a voltage pulse is generated which kicks back into the inductor to reduce the inductor current. The voltage across the Josephson junction is, therefore, a one bit digital representation of the analog signal. This one bit digital signal is converted to a multi-bit digital signal preferably by a decimator having superconducting circuits which reduce the frequency of the multi-bit digital signal to a frequency which can be further processed by semiconductor processors. Preferably, a weighting function is utilized in a conversion to improve accuracy.
摘要翻译：超导Σ-Δ模数转换器利用超导电感器作为积分器，并且将约瑟夫逊结串联连接在电感器和地之间作为量化器。 SQUID以选定的GHz频率产生采样脉冲，这增加了流过约瑟夫逊结的电感电流。当通过约瑟夫逊结的组合电流超过约瑟夫逊结的临界电流时，产生电压脉冲，其将回到电感器中以减小电感器电流。因此，约瑟夫逊结上的电压是模拟信号的一位数字表示。该一比特数字信号优选地被具有超导电路的抽取器转换成多位数字信号，该超导电路将多比特数字信号的频率降低到可由半导体处理器进一步处理的频率。优选地，在转换中利用加权函数来提高精度。

7. 发明授权

US06215288B1 Ultra-low power switching regulator method and apparatus 有权
标题翻译：超低功率开关调节器的方法和装置
公开(公告)号：US06215288B1
公开(公告)日：2001-04-10
申请号：US09513338
申请日：2000-02-25
申请人： Carl A. Ramsey , Eric H. Naviasky
发明人： Carl A. Ramsey , Eric H. Naviasky
IPC分类号： G05F1613
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： A low-power controller for a discontinuous switched mode power converter. The controller has an inductor current sensing circuit to measure the inductor current flowing through an inductive charge storage element as well as an output voltage sensing circuit to monitor output voltage. The controller monitors both the converter output voltage and the inductor current and uses this information to modulate a peak inductor current trip point and controller switching frequency according to a control law curve in order to regulate converter output voltage. The controller prevents the switching frequency from falling below a predetermined minimum frequency. The control law curve is selectable to specify controller operation according to a desired combination of minimum switching frequency and maximum peak inductor current.
摘要翻译：用于不连续开关模式功率转换器的低功率控制器。控制器具有电感电流检测电路，用于测量流过感应电荷存储元件的电感电流以及输出电压检测电路，以监测输出电压。控制器监视转换器输出电压和电感电流，并使用该信息根据控制律曲线调制峰值电感器电流跳变点和控制器开关频率，以调节转换器输出电压。控制器防止开关频率降低到预定的最小频率以下。根据最小开关频率和最大峰值电感电流的期望组合，可选择控制律曲线以指定控制器运行。

8. 发明授权

US5084868A Common bus multinode sensor system 失效
标题翻译：公共汽车多节点传感器系统
公开(公告)号：US5084868A
公开(公告)日：1992-01-28
申请号：US193698
申请日：1988-05-13
申请人： Thomas F. Kelly , Eric H. Naviasky , Daniel W. Jefferies , William P. Evans , John R. Smith
发明人： Thomas F. Kelly , Eric H. Naviasky , Daniel W. Jefferies , William P. Evans , John R. Smith
IPC分类号： G08C15/04
CPC分类号： G08C15/04
摘要： The present invention is a multimode sensor system that transmits power down a common bus coaxial cable typically using an alternating current power source. Each remote unit connected to the coaxial cable and through an isolation transformer converts the alternating current power to direct current power for an integrated circuit bus interface. The interface is connected to the sensors. The interface is externally pin programmable to provide a carrier at a frequency for a channel assigned to the remote unit. The carrier is provided by a ripple counter producing a frequency divided signal compared to a fixed reference frequency, where the result of the comparison controls a voltage controlled oscillator. When plural low frequency analog signals are to be transmitted over the common bus, an on-chip multiplexer multiplexes the signals to an off-chip, external analog-to-digital converter. The analog-to-digital converter loads an on chip parallel to serial register that applies each bit of the sampled signal serially to an on chip Manchester encoder. The encoder modifies the input voltage of the voltage controlled oscillator operating at the carrier frequency. The oscillator signal is applied to the coaxial cable. Receivers at the end of the coaxial cable are each tunable to a designated carrier frequency and each decode the respective encoded signal. If a high frequency analog signal is supplied to the voltage controlled oscillator, the carrier is modulated by the high frequency signal and the receiver demodulates the signal. The integrated circuit is arranged so that the digital circuitry is generally isolated from the analog circuitry so noise immunity is enhanced.
摘要翻译：本发明是一种多模传感器系统，其通常使用交流电源将公共总线同轴电缆发射功率。连接到同轴电缆并通过隔离变压器的每个远程单元将交流电力转换为用于集成电路总线接口的直流电力。接口连接到传感器。该接口是外部可编程的，以便为分配给远程单元的通道提供一个频率的载波。载波由波纹计数器提供，产生与固定参考频率相比的分频信号，其中比较结果控制压控振荡器。当通过公共总线传输多个低频模拟信号时，片上多路复用器将信号复用到片外外部模数转换器。模数转换器将片上并行串行寄存器加载，将串行采样信号的每一位应用于片上曼彻斯特编码器。编码器修改以载波频率工作的压控振荡器的输入电压。振荡器信号施加到同轴电缆。同轴电缆末端的接收机各自可调谐到指定的载波频率，并且每个解码相应的编码信号。如果将高频模拟信号提供给压控振荡器，则载波由高频信号调制，并且接收机解调该信号。集成电路被布置成使得数字电路通常与模拟电路隔离，因此增强了抗噪声性。

9. 发明授权

US4722073A Magnetoresistive random access cross-tie memory architecture and signal processing system 失效
标题翻译：磁阻随机访问交叉内存架构和信号处理系统
公开(公告)号：US4722073A
公开(公告)日：1988-01-26
申请号：US795284
申请日：1985-11-05
申请人： Donald R. Lampe , Mark A. Mentzer , Eric H. Naviasky
发明人： Donald R. Lampe , Mark A. Mentzer , Eric H. Naviasky
IPC分类号： G11C19/08
CPC分类号： G11C19/0875 , G11C19/0841 , G11C19/0866
摘要： A magnetoresistive random access memory array and signal processing system which provides an improved signal to noise ratio. The basic memory complex associated with the storage of a single binary digit is a quad of memory elements or cells which are addressed in complementary fashion. The enhanced read-out signal discrimination is had by utilizing a double-correlated double-sampling differential signal processing system in which complementary data is serially passed through the same path with repeated high-speed differencing which greatly reduces nonuniformity fixed patterns as well as correlated low frequency temporal noise.
摘要翻译：磁阻随机存取存储器阵列和提供改善的信噪比的信号处理系统。与存储单个二进制数字相关联的基本存储器复合体是以互补方式寻址的存储器元件或单元的四分之一。通过利用双重相关双采样差分信号处理系统实现增强的读出信号鉴别，其中互补数据通过重复的高速差分串行地通过相同的路径，这大大减少了不均匀性固定模式以及相关的低频率时间噪声。

10. 发明授权

US4506171A Latching type comparator 失效
标题翻译：锁存型比较器
公开(公告)号：US4506171A
公开(公告)日：1985-03-19
申请号：US454215
申请日：1982-12-29
申请人： William P. Evans , Robert J. McCabe , Eric H. Naviasky
发明人： William P. Evans , Robert J. McCabe , Eric H. Naviasky
IPC分类号： H03K3/2885 , H03K5/08 , H03K19/086
CPC分类号： H03K3/2885
摘要： An improved latching-type comparator operative in a selected one of two exclusive states is disclosed. In one state, the operational state, a gain stage is rendered operative to amplify at least one intermediate current signal generated by an input stage in response to the comparison of a pair of input signals. At least one drive current signal is generated by the gain stage in response to the comparison and is buffered by a corresponding buffer stage to render both an output signal and a signal representative thereof. In the other state, a latch stage is rendered operative unresponsive to the comparison and governed by the signal representative of the output signal to sustain the drive current signal in a state to latch the output signal. A switching stage governed by at least one latch signal effects the selection between the gain and latch stages by conducting operating current exclusively from the selected stage to a constant current stage. An independent second constant current stage provides current for the input stage to maintain its operation continuously independent of the selected date of the comparator.
摘要翻译：公开了一种改进的锁存型比较器，其操作在两种独占状态中选定的一种状态。在一种状态下，响应于一对输入信号的比较，增益级可操作以放大由输入级产生的至少一个中间电流信号。响应于比较，由增益级产生至少一个驱动电流信号，并且被相应的缓冲级缓冲以呈现输出信号和表示其的信号。在另一状态下，锁存级使得操作对比较无响应，并且由表示输出信号的信号来控制，以在将锁存输出信号的状态下维持驱动电流信号。由至少一个锁存信号控制的开关级通过仅将选定级的工作电流传导到恒定电流级来实现增益和锁存级之间的选择。独立的第二恒定电流级为输入级提供电流，以保持其运行，而不依赖于比较器的选定日期。

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