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    • 3. 发明授权
    • Low power dissipation, high linearity transmitter
    • 功耗低,线性度高
    • US06608860B1
    • 2003-08-19
    • US09434592
    • 1999-11-05
    • Eric H. NaviaskyMartin J. Mengele
    • Eric H. NaviaskyMartin J. Mengele
    • H04L2500
    • H04L25/0266
    • An improved transmitter capable of achieving high linearity with minimal power dissipation is disclosed, comprising a digital phase splitter and an output stage. The digital phase splitter includes a positive phase digital-to-analog converter (DAC) for converting the positive phase portion of a set of input digital data into an analog signal, and a negative phase DAC for converting the negative phase portion of the set of input digital data into another analog signal. The analog signals from the phase splitter are passed to the output stage for transmission onto a transmission medium. The transmitter may be operated in low power dissipation mode. Because the phases of the input digital signal are split in the digital domain prior to the output stage, the output stage experiences minimal crossover distortion. Consequently, the transmitter is able to minimize power dissipation without suffering from poor linearity performance.
    • 公开了一种能够以最小功耗实现高线性度的改进的发射机,包括数字分相器和输出级。 数字分相器包括用于将一组输入数字数据的正相部分转换为模拟信号的正相数模转换器(DAC),以及用于将该组输出数字数据的负相位部分转换为 将数字数据输入到另一个模拟信号。 来自分相器的模拟信号被传送到输出级,以便传输到传输介质上。 发射机可以在低功耗模式下工作。 由于输入数字信号的相位在输出级之前在数字域中分离,所以输出级经历最小的交叉失真。 因此,发射机能够最小化功率耗散,而不会受到线性性能的差。
    • 4. 发明授权
    • Two loop superconducting sigma-delta analog-to-digital converters
    • 双回路超导Σ-Δ模数转换器
    • US5198815A
    • 1993-03-30
    • US807040
    • 1991-12-12
    • John X. PrzybyszDonald L. MillerEric H. Naviasky
    • John X. PrzybyszDonald L. MillerEric H. Naviasky
    • H03M3/02
    • H03M3/438H03M3/43
    • A two-loop superconducting sigma-delta analog-to-digital converter includes a first superconducting inductor to which the analog signal is applied. A resistor converts to current in the first inductor to a voltage which is applied to a second superconducting inductor. The current in the second inductor, which increases quadradically with time, is applied to an overdamped Josephson junction which kicks back a single quantum voltage pulse each time its critical current is exceeded. This pulse reduces the current in the second inductor and serves as a digital ONE output. The pulses are also applied to an underdamped Josephson junction in a feedback pulse generator which latches at its gap voltage for the remainder of a half cycle of an ac bias current. This provides a voltage source for the primary of a superconducting transformer having a mutual inductance which produces sufficient flux in the secondary to cause a SQUID to generate in response to each pulse from the quantizer a selected number of feedback pulses which are applied to the first inductor.
    • 双回路超导Σ-Δ模数转换器包括施加模拟信号的第一超导电感器。 电阻器将第一电感器中的电流转换为施加到第二超导电感器的电压。 随着时间的推移,第二电感器中的电流逐渐增加,被施加到过阻尼的约瑟夫逊结,每当超过其临界电流时,它将踢回单个量子电压脉冲。 该脉冲降低了第二电感器中的电流,并且用作数字ONE输出。 脉冲也被施加到反馈脉冲发生器中的欠阻尼约瑟夫逊结,该反馈脉冲发生器在交流偏置电流的剩余半周期内以其间隙电压锁存。 这为具有互感的超导变压器的初级电压提供电压源,该互感器在辅助电路中产生足够的通量,以使SQUID响应于来自量化器的每个脉冲而产生选定数量的反馈脉冲,该反馈脉冲施加到第一电感器 。
    • 5. 发明授权
    • Highly linear sigma-delta modulator having graceful degradation of signal-to-noise ratio in overload condition
    • 高度线性的Σ-Δ调制器在过载条件下具有信噪比的优雅降低
    • US06331833B1
    • 2001-12-18
    • US09488660
    • 2000-01-20
    • Eric H. NaviaskyMichael M. HuffordJeremy Lubkin
    • Eric H. NaviaskyMichael M. HuffordJeremy Lubkin
    • H03M106
    • H03M3/366H03M3/458
    • A multi-bit analog-to-digital converter architecture, which during normal operation behaves like a single-bit converter, thus sharing the high linearity and low distortion properties of the simpler system. When a high input signal is applied, a second bit is triggered and the system behaves like a more complex multi-bit system, providing system stability where a single-bit comparator would overload and the system would become unstable. During normal operation, a single-bit converter is sufficient to stabilize the system. When the input is a large, sustained signal (relative to the full scale of the converter) this single-bit approach is not sufficient to maintain system stability. Thus, if the input to the analog-to-digital converter is close to its maximum or minimum range (implying a large positive or negative input signal) a second bit is triggered, providing stable linearity where the signal-to-noise ratio of a conventional sigma-delta converter would rapidly drop off.
    • 在正常操作期间,多位模数转换器架构表现得像单位转换器,从而共享更简单系统的高线性度和低失真特性。 当施加高输入信号时,触发第二个位,并且系统的行为就像一个更复杂的多位系统,提供系统稳定性,其中单位比较器将过载并且系统变得不稳定。 在正常操作期间,单位转换器足以稳定系统。 当输入是一个大的持续信号(相对于转换器的满刻度)时,这种单位方式不足以维持系统的稳定性。 因此,如果模数转换器的输入接近其最大或最小范围(意味着大的正或负输入信号),则触发第二位,从而提供稳定的线性度,其中信号 - 噪声比为 传统的Σ-Δ转换器将迅速下降。
    • 7. 发明授权
    • Superconducting sigma-delta analog-to-digital converter
    • 超导Σ-Δ模数转换器
    • US5140324A
    • 1992-08-18
    • US710856
    • 1991-06-06
    • John X. PrzybyszDonald L. MillerEric H. Naviasky
    • John X. PrzybyszDonald L. MillerEric H. Naviasky
    • H03M3/02
    • H03M3/456H03M3/43
    • A superconducting sigma-delta analog-to-digital converter utilizes a superconducting inductor as the integrator and a Josephson junction connected in series between the inductor and ground as the quantizer. A SQUID generates sampling pulses at a selected GHz frequency which add to the inductor current flowing through the Josephson junction. When the combined current through the Josephson junction exceeds the critical current of the Josephson junction, a voltage pulse is generated which kicks back into the inductor to reduce the inductor current. The voltage across the Josephson junction is, therefore, a one bit digital representation of the analog signal. This one bit digital signal is converted to a multi-bit digital signal preferably by a decimator having superconducting circuits which reduce the frequency of the multi-bit digital signal to a frequency which can be further processed by semiconductor processors. Preferably, a weighting function is utilized in a conversion to improve accuracy.
    • 超导Σ-Δ模数转换器利用超导电感器作为积分器,并且将约瑟夫逊结串联连接在电感器和地之间作为量化器。 SQUID以选定的GHz频率产生采样脉冲,这增加了流过约瑟夫逊结的电感电流。 当通过约瑟夫逊结的组合电流超过约瑟夫逊结的临界电流时,产生电压脉冲,其将回到电感器中以减小电感器电流。 因此,约瑟夫逊结上的电压是模拟信号的一位数字表示。 该一比特数字信号优选地被具有超导电路的抽取器转换成多位数字信号,该超导电路将多比特数字信号的频率降低到可由半导体处理器进一步处理的频率。 优选地,在转换中利用加权函数来提高精度。
    • 9. 发明授权
    • Ultra-low power switching regulator method and apparatus
    • 超低功率开关调节器的方法和装置
    • US06215288B1
    • 2001-04-10
    • US09513338
    • 2000-02-25
    • Carl A. RamseyEric H. Naviasky
    • Carl A. RamseyEric H. Naviasky
    • G05F1613
    • H02M3/1588Y02B70/1466
    • A low-power controller for a discontinuous switched mode power converter. The controller has an inductor current sensing circuit to measure the inductor current flowing through an inductive charge storage element as well as an output voltage sensing circuit to monitor output voltage. The controller monitors both the converter output voltage and the inductor current and uses this information to modulate a peak inductor current trip point and controller switching frequency according to a control law curve in order to regulate converter output voltage. The controller prevents the switching frequency from falling below a predetermined minimum frequency. The control law curve is selectable to specify controller operation according to a desired combination of minimum switching frequency and maximum peak inductor current.
    • 用于不连续开关模式功率转换器的低功率控制器。 控制器具有电感电流检测电路,用于测量流过感应电荷存储元件的电感电流以及输出电压检测电路,以监测输出电压。 控制器监视转换器输出电压和电感电流,并使用该信息根据控制律曲线调制峰值电感器电流跳变点和控制器开关频率,以调节转换器输出电压。 控制器防止开关频率降低到预定的最小频率以下。 根据最小开关频率和最大峰值电感电流的期望组合,可选择控制律曲线以指定控制器运行。
    • 10. 发明授权
    • Common bus multinode sensor system
    • 公共汽车多节点传感器系统
    • US5084868A
    • 1992-01-28
    • US193698
    • 1988-05-13
    • Thomas F. KellyEric H. NaviaskyDaniel W. JefferiesWilliam P. EvansJohn R. Smith
    • Thomas F. KellyEric H. NaviaskyDaniel W. JefferiesWilliam P. EvansJohn R. Smith
    • G08C15/04
    • G08C15/04
    • The present invention is a multimode sensor system that transmits power down a common bus coaxial cable typically using an alternating current power source. Each remote unit connected to the coaxial cable and through an isolation transformer converts the alternating current power to direct current power for an integrated circuit bus interface. The interface is connected to the sensors. The interface is externally pin programmable to provide a carrier at a frequency for a channel assigned to the remote unit. The carrier is provided by a ripple counter producing a frequency divided signal compared to a fixed reference frequency, where the result of the comparison controls a voltage controlled oscillator. When plural low frequency analog signals are to be transmitted over the common bus, an on-chip multiplexer multiplexes the signals to an off-chip, external analog-to-digital converter. The analog-to-digital converter loads an on chip parallel to serial register that applies each bit of the sampled signal serially to an on chip Manchester encoder. The encoder modifies the input voltage of the voltage controlled oscillator operating at the carrier frequency. The oscillator signal is applied to the coaxial cable. Receivers at the end of the coaxial cable are each tunable to a designated carrier frequency and each decode the respective encoded signal. If a high frequency analog signal is supplied to the voltage controlled oscillator, the carrier is modulated by the high frequency signal and the receiver demodulates the signal. The integrated circuit is arranged so that the digital circuitry is generally isolated from the analog circuitry so noise immunity is enhanced.
    • 本发明是一种多模传感器系统,其通常使用交流电源将公共总线同轴电缆发射功率。 连接到同轴电缆并通过隔离变压器的每个远程单元将交流电力转换为用于集成电路总线接口的直流电力。 接口连接到传感器。 该接口是外部可编程的,以便为分配给远程单元的通道提供一个频率的载波。 载波由波纹计数器提供,产生与固定参考频率相比的分频信号,其中比较结果控制压控振荡器。 当通过公共总线传输多个低频模拟信号时,片上多路复用器将信号复用到片外外部模数转换器。 模数转换器将片上并行串行寄存器加载,将串行采样信号的每一位应用于片上曼彻斯特编码器。 编码器修改以载波频率工作的压控振荡器的输入电压。 振荡器信号施加到同轴电缆。 同轴电缆末端的接收机各自可调谐到指定的载波频率,并且每个解码相应的编码信号。 如果将高频模拟信号提供给压控振荡器,则载波由高频信号调制,并且接收机解调该信号。 集成电路被布置成使得数字电路通常与模拟电路隔离,因此增强了抗噪声性。