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1. 发明授权

US07579886B2 Phase locked loop with adaptive phase error compensation 有权
标题翻译：具有自适应相位误差补偿的锁相环
公开(公告)号：US07579886B2
公开(公告)日：2009-08-25
申请号：US11608213
申请日：2006-12-07
申请人： Michael M. Hufford , Eric Naviasky , Tony Caviglia
发明人： Michael M. Hufford , Eric Naviasky , Tony Caviglia
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , H03L7/0891 , H03L7/1976
摘要： An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.
摘要翻译：自适应锁相环（PLL）电路产生具有参考参考信号的频率的频率的输出信号。 PLL电路包括被配置为根据频率控制信号产生输出信号的振荡器，以及被配置为产生从输出信号导出的反馈信号的处理电路。提供可调移位电路来对反馈信号进行时移。 PLL还包括相位比较电路，被配置为产生指示时移反馈信号和参考信号之间的相位误差的相位误差信号，以及配置为基于相位误差信号产生频率控制信号的控制电路。可调移位电路根据相位误差信号调整时移量以使反馈信号进行时移。

2. 发明授权

US06331833B1 Highly linear sigma-delta modulator having graceful degradation of signal-to-noise ratio in overload condition 有权
标题翻译：高度线性的Σ-Δ调制器在过载条件下具有信噪比的优雅降低
公开(公告)号：US06331833B1
公开(公告)日：2001-12-18
申请号：US09488660
申请日：2000-01-20
申请人： Eric H. Naviasky , Michael M. Hufford , Jeremy Lubkin
发明人： Eric H. Naviasky , Michael M. Hufford , Jeremy Lubkin
IPC分类号： H03M106
CPC分类号： H03M3/366 , H03M3/458
摘要： A multi-bit analog-to-digital converter architecture, which during normal operation behaves like a single-bit converter, thus sharing the high linearity and low distortion properties of the simpler system. When a high input signal is applied, a second bit is triggered and the system behaves like a more complex multi-bit system, providing system stability where a single-bit comparator would overload and the system would become unstable. During normal operation, a single-bit converter is sufficient to stabilize the system. When the input is a large, sustained signal (relative to the full scale of the converter) this single-bit approach is not sufficient to maintain system stability. Thus, if the input to the analog-to-digital converter is close to its maximum or minimum range (implying a large positive or negative input signal) a second bit is triggered, providing stable linearity where the signal-to-noise ratio of a conventional sigma-delta converter would rapidly drop off.
摘要翻译：在正常操作期间，多位模数转换器架构表现得像单位转换器，从而共享更简单系统的高线性度和低失真特性。当施加高输入信号时，触发第二个位，并且系统的行为就像一个更复杂的多位系统，提供系统稳定性，其中单位比较器将过载并且系统变得不稳定。在正常操作期间，单位转换器足以稳定系统。当输入是一个大的持续信号（相对于转换器的满刻度）时，这种单位方式不足以维持系统的稳定性。因此，如果模数转换器的输入接近其最大或最小范围（意味着大的正或负输入信号），则触发第二位，从而提供稳定的线性度，其中信号 - 噪声比为传统的Σ-Δ转换器将迅速下降。

3. 发明申请

US20080136532A1 PHASE LOCKED LOOP WITH ADAPTIVE PHASE ERROR COMPENSATION 有权
标题翻译：相位锁定环路，具有自适应相位误差补偿
公开(公告)号：US20080136532A1
公开(公告)日：2008-06-12
申请号：US11608213
申请日：2006-12-07
申请人： Michael M. HUFFORD , Eric Naviasky , Tony Caviglia
发明人： Michael M. HUFFORD , Eric Naviasky , Tony Caviglia
IPC分类号： H03L7/089 , H03L7/08 , H03L7/085
CPC分类号： H03L7/081 , H03L7/0891 , H03L7/1976
摘要： An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.
摘要翻译：自适应锁相环（PLL）电路产生具有参考参考信号的频率的频率的输出信号。 PLL电路包括被配置为根据频率控制信号产生输出信号的振荡器，以及被配置为产生从输出信号导出的反馈信号的处理电路。提供可调移位电路来对反馈信号进行时移。 PLL还包括相位比较电路，被配置为产生指示时移反馈信号和参考信号之间的相位误差的相位误差信号，以及配置为基于相位误差信号产生频率控制信号的控制电路。可调移位电路根据相位误差信号调整时移量以使反馈信号进行时移。

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