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1. 发明授权

US08151031B2 Local memories with permutation functionality for digital signal processors 有权
标题翻译：具有数字信号处理器置换功能的本地存储器
公开(公告)号：US08151031B2
公开(公告)日：2012-04-03
申请号：US12399719
申请日：2009-03-06
申请人： Eric Biscondi , David J. Hoyle , Tod D. Wolf
发明人： Eric Biscondi , David J. Hoyle , Tod D. Wolf
IPC分类号： G06F12/00
CPC分类号： G06F15/7857 , G06F9/30018 , G06F9/30032 , G06F9/3885
摘要： A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.
摘要翻译：根据具有本地存储器的集群架构的数字信号处理器（DSP）协处理器。架构中的每个集群包括多个子集群，每个子集群能够执行一个或两个指令，这些指令可以专门针对特定的DSP操作。每个集群中的子集群通过集群中的交叉开关与全局内存资源进行通信。子集群中的一个或多个具有专用本地存储器，其可以以随机存取方式，向量存取方式或以流或堆栈方式访问。本地存储器被布置为多个存储体。响应于某些向量访问指令，可以根据存储在寄存器中的置换模式，在写入之前在存储体之间排列输入数据，或者在从存储体读取之后被置换。

2. 发明申请

US20090254718A1 Local Memories with Permutation Functionality for Digital Signal Processors 有权
标题翻译：具有数字信号处理器置换功能的本地存储器
公开(公告)号：US20090254718A1
公开(公告)日：2009-10-08
申请号：US12399719
申请日：2009-03-06
申请人： Eric Biscondi , David J. Hoyle , Tod D. Wolf
发明人： Eric Biscondi , David J. Hoyle , Tod D. Wolf
IPC分类号： G06F15/76 , G06F12/06 , G06F12/00 , G06F9/02
CPC分类号： G06F15/7857 , G06F9/30018 , G06F9/30032 , G06F9/3885
摘要： A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.
摘要翻译：根据具有本地存储器的集群架构的数字信号处理器（DSP）协处理器。架构中的每个集群包括多个子集群，每个子集群能够执行一个或两个指令，这些指令可以专门针对特定的DSP操作。每个集群中的子集群通过集群中的交叉开关与全局内存资源进行通信。子集群中的一个或多个具有专用本地存储器，其可以以随机存取方式，向量存取方式或以流或堆栈方式访问。本地存储器被布置为多个存储体。响应于某些向量访问指令，可以根据存储在寄存器中的置换模式，在写入之前在存储体之间排列输入数据，或者在从存储体读取之后被置换。

3. 发明授权

US07995640B2 Dynamic interpolation location 有权
标题翻译：动态插补位置
公开(公告)号：US07995640B2
公开(公告)日：2011-08-09
申请号：US11931906
申请日：2007-10-31
申请人： Pierre Bertrand , David J. Hoyle , Eric Biscondi
发明人： Pierre Bertrand , David J. Hoyle , Eric Biscondi
IPC分类号： H04B1/00
CPC分类号： H04B1/707
摘要： Apparatus and method for optimizing interpolation in the despreader data-path of a wireless telecommunications network employing Code Division Multiple Access (CDMA) technology. A base station dynamically evaluates its configuration to determine an interpolator location. The location of the interpolator in a despreader data-path is dynamically selected. A received signal is interpolated. The despread received signals are combined, and further processing is applied to the combined signal. To enhance system performance, the interpolator may, be located at least to perform chip-sample interpolation per antenna stream at chip rate, chip-sample interpolation per user at chip rate, or symbol-sample interpolation per user at sub-symbol rate.
摘要翻译：用于优化使用码分多址（CDMA）技术的无线电信网络的解扩器数据路径内插的装置和方法。基站动态地评估其配置以确定内插器位置。动态地选择内插器在解扩器数据路径中的位置。接收到的信号被内插。解扩后的接收信号进行组合，对组合信号进行进一步处理。为了提高系统性能，插值器可以至少位于以码片速率对每个天线流进行芯片样本插值，以码片速率对每个用户进行芯片样本插值，或以每个用户以子符号率进行符号样本内插。

4. 发明申请

US20110029756A1 Method and System for Decoding Low Density Parity Check Codes 有权
标题翻译：解密低密度奇偶校验码的方法和系统
公开(公告)号：US20110029756A1
公开(公告)日：2011-02-03
申请号：US12510899
申请日：2009-07-28
申请人： Eric Biscondi , David Hoyle , Tod David Wolf
发明人： Eric Biscondi , David Hoyle , Tod David Wolf
IPC分类号： H03M13/05 , G06F15/80 , G06F9/02 , G06F11/10
CPC分类号： H03M13/116 , H03M13/1114 , H03M13/1117 , H03M13/112 , H03M13/1165 , H03M13/1188 , H03M13/3715 , H03M13/3723 , H03M13/3753 , H03M13/47 , H03M13/616 , H03M13/6544 , H03M13/658 , H03M13/6583
摘要： A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.
摘要翻译：一种用于根据具有m×j个奇偶校验矩阵H的低密度奇偶校验（LDPC）码编码的数据流中的码字进行解码的方法，通过基于码字中的符号来初始化具有软值的可变节点，其中，图形表示 H包括m个校验节点和j个变量节点，并且其中校验节点m向变量节点j提供行值估计，并且如果H（m，j）包含校验节点j，变量节点j向校验节点m提供列值估计 1，计算每个校验节点的行值估计，其中仅计算提供给校验节点的列值估计的子集的幅度，基于所计算的行值估计来计算每个变量节点的软值，确定码字是否被解码基于软值，并且当码字被解码时终止解码。

5. 发明申请

US20100005372A1 METHOD AND APPARATUS FOR IMPROVING TRELLIS DECODING 审中-公开
标题翻译：改进色拉解码的方法和装置
公开(公告)号：US20100005372A1
公开(公告)日：2010-01-07
申请号：US12496527
申请日：2009-07-01
申请人： Peter R. Dent , Eric Biscondi , David Hoyle
发明人： Peter R. Dent , Eric Biscondi , David Hoyle
IPC分类号： H03M13/23 , G06F11/10
CPC分类号： H03M13/41 , H03M13/395
摘要： A digital signal processor for decoding Trellis based channel encoding stages based on radix-4 stages comprising means for rearranging the input and output data in Radix-4 Viterbi decoding to make inter-stage Trellis data movement suitable for use in the digital signal processor.
摘要翻译：一种用于基于基4级解码基于网格的信道编码级的数字信号处理器，包括用于在基数-4维特比解码中重新排列输入和输出数据的装置，以使适合于在数字信号处理器中使用的阶段间格间数据移动。

6. 发明申请

US20100002793A1 METHOD AND APPARATUS FOR CODING RELATING TO A FORWARD LOOP 审中-公开
标题翻译：用于与前向环路相关的编码的方法和装置
公开(公告)号：US20100002793A1
公开(公告)日：2010-01-07
申请号：US12496538
申请日：2009-07-01
申请人： Peter R. Dent , Eric Biscondi , David Hoyle
发明人： Peter R. Dent , Eric Biscondi , David Hoyle
IPC分类号： H04L5/12
CPC分类号： H03M13/4107 , H03M13/395 , H03M13/4169
摘要： A high data width accelerator, comprising computer instructions for calculating at least a portion of a trace-back during a trellis computation, wherein the calculation allows faster trace-back
摘要翻译：高数据宽度加速器，包括用于在网格计算期间计算回溯的至少一部分的计算机指令，其中所述计算允许更快的追溯

7. 发明授权

US08880855B2 Dual register data path architecture with registers in a data file divided into groups and sub-groups 有权
标题翻译：双寄存器数据路径架构，将数据文件中的寄存器分为组和子组
公开(公告)号：US08880855B2
公开(公告)日：2014-11-04
申请号：US13233025
申请日：2011-09-15
申请人： Timothy D Anderson , Duc Quang Bui , Eric Biscondi , Shriram D Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
发明人： Timothy D Anderson , Duc Quang Bui , Eric Biscondi , Shriram D Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
IPC分类号： G06F9/34 , H03K21/00 , G06F1/32 , H03K19/00 , G06F7/483 , G06F12/02 , G06F9/30
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
摘要翻译：处理器包括第一和第二执行单元，每个执行单元被配置为在固定点操作数上执行第一类型的乘法指令，并且在浮点操作数上执行第二类型的乘法指令。处理器的寄存器文件将操作数存储在寄存器中，每个可操作数可由用于执行第一和第二类操作的指令来寻址。指令解码单元响应于第一类型的至少一个乘法指令和第二类型的至少一个乘法指令，同时使第一组寄存器和第一执行单元之间的第一数据路径和以使得能够在第二组寄存器和第二执行单元之间建立第二数据路径。

8. 发明申请

US20120079247A1 DUAL REGISTER DATA PATH ARCHITECTURE 有权
标题翻译：双重注册数据路径架构
公开(公告)号：US20120079247A1
公开(公告)日：2012-03-29
申请号：US13233025
申请日：2011-09-15
申请人： Timothy D. Anderson , Duc Quang Bui , Eric Biscondi , Shriram D. Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
发明人： Timothy D. Anderson , Duc Quang Bui , Eric Biscondi , Shriram D. Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
IPC分类号： G06F9/30
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
摘要翻译：处理器包括第一和第二执行单元，每个执行单元被配置为在固定点操作数上执行第一类型的乘法指令，并且在浮点操作数上执行第二类型的乘法指令。处理器的寄存器文件将操作数存储在寄存器中，每个可操作数可由用于执行第一和第二类操作的指令来寻址。指令解码单元响应于第一类型的至少一个乘法指令和第二类型的至少一个乘法指令，同时使第一组寄存器和第一执行单元之间的第一数据路径和以使得能够在第二组寄存器和第二执行单元之间建立第二数据路径。

9. 发明授权

US07218669B2 Wireless communication system operating in response in part to time signals from the global position satellite system 有权
标题翻译：无线通信系统部分响应来自全球定位卫星系统的时间信号
公开(公告)号：US07218669B2
公开(公告)日：2007-05-15
申请号：US10174376
申请日：2002-06-18
申请人： Pierre Bertrand , Sundararajan Sriram , Eric Biscondi , Frank Honore
发明人： Pierre Bertrand , Sundararajan Sriram , Eric Biscondi , Frank Honore
IPC分类号： H04B1/38
CPC分类号： H04B1/7073 , H04B2201/70715
摘要： A wireless communication system (10). The system comprises a transceiver (20), and the transceiver comprises a code counter (LCSTC 22c) and a clock oscillator (26) for advancing a count in the code counter. The transceiver further comprises circuitry (30) for receiving a time message based on a system time external from the transceiver and circuitry (28) for determining a system time count and for storing the system time count to the code counter in response to the time message. Further, code counter continues to be advanced from the system time count in response to the clock oscillator. The transceiver further comprises circuitry (28) for repeatedly evaluating the count in the code counter, after advancement from the system time count, to ascertain whether the count has drifted to an inaccurate count. Lastly, the transceiver further comprises circuitry (28), responsive to detecting an inaccurate count, for adjusting the inaccurate count to a perceived accurate count.
摘要翻译：一种无线通信系统（10）。该系统包括收发器（20），并且收发器包括用于前进代码计数器中的计数的代码计数器（LCSTC 22c）和时钟振荡器（26）。收发器还包括电路（30），用于基于来自收发器和电路（28）的外部系统时间接收时间消息，用于确定系统时间计数并且响应于时间消息将系统时间计数存储到代码计数器。此外，响应于时钟振荡器，代码计数器继续从系统时间计数中提前。收发器还包括电路（28），用于在从系统时间计数开始之后重复地评估代码计数器中的计数，以确定计数是否已经偏移到不准确的计数。最后，收发器还包括响应于检测不准确计数的电路（28），用于将不准确的计数调整为感知到的精确计数。

10. 发明授权

US08392789B2 Method and system for decoding low density parity check codes 有权
标题翻译：解码低密度奇偶校验码的方法和系统
公开(公告)号：US08392789B2
公开(公告)日：2013-03-05
申请号：US12510899
申请日：2009-07-28
申请人： Eric Biscondi , David Hoyle , Tod David Wolf
发明人： Eric Biscondi , David Hoyle , Tod David Wolf
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1114 , H03M13/1117 , H03M13/112 , H03M13/1165 , H03M13/1188 , H03M13/3715 , H03M13/3723 , H03M13/3753 , H03M13/47 , H03M13/616 , H03M13/6544 , H03M13/658 , H03M13/6583
摘要： A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.
摘要翻译：一种用于根据具有m×j个奇偶校验矩阵H的低密度奇偶校验（LDPC）码编码的数据流中的码字进行解码的方法，通过基于码字中的符号来初始化具有软值的可变节点，其中，图形表示 H包括m个校验节点和j个变量节点，并且其中校验节点m向变量节点j提供行值估计，并且如果H（m，j）包含校验节点j，变量节点j向校验节点m提供列值估计 1，计算每个校验节点的行值估计，其中仅计算提供给校验节点的列值估计的子集的幅度，基于所计算的行值估计来计算每个变量节点的软值，确定码字是否被解码基于软值，并且当码字被解码时终止解码。

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