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1. 发明授权

US09189456B2 Technique for optimization and re-use of hardware in the implementation of instructions used in Viterbi and turbo decoding, using carry save arithmetic 有权
标题翻译：技术优化和重用硬件在执行指令中使用维特比和turbo解码，采用进位保存算术
公开(公告)号：US09189456B2
公开(公告)日：2015-11-17
申请号：US13916810
申请日：2013-06-13
申请人： Timothy D Anderson , Shriram D Moharil
发明人： Timothy D Anderson , Shriram D Moharil
IPC分类号： G06F7/50 , G06F17/12 , H03M13/39 , H03M13/41 , H03M13/00
CPC分类号： G06F17/12 , H03M13/3922 , H03M13/395 , H03M13/4107 , H03M13/6502 , H03M13/6511 , H03M13/6586
摘要： The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2−b2+c2) with (x2+y2+z2); and (a3+b3−c3) with (x3+y3+z3); implementing an efficient method of computing (a4−b4−c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.
摘要翻译：本发明提供了一种用于在使用进位保存算术实现维特比和Turbo解码器中优化和重用硬件的手段。每个目标申请的成功规定要求面对两个主要问题。这些是：将求和项（a2-b2 + c2）与（x2 + y2 + z2）的计算合并; 和（a3 + b3-c3）与（x3 + y3 + z3）实现有效的计算方法（a4-b4-c4）; 并将该计算与（x4 + y4 + z4）合并。本发明解决了这两个问题，并且成功地将维特比指令与实现Turbo指令所需的硬件的完全重用相结合。通过有效地采用进位保存算法来优化两类指令所需的硬件。

2. 发明申请

US20110060782A1 Hardware Implementation of a Galois Field Multiplier 有权
标题翻译：伽罗瓦域乘数的硬件实现
公开(公告)号：US20110060782A1
公开(公告)日：2011-03-10
申请号：US12875732
申请日：2010-09-03
申请人： Shriram D. Moharil , Rejitha Nair
发明人： Shriram D. Moharil , Rejitha Nair
IPC分类号： G06F7/60
CPC分类号： G06F7/724
摘要： An embodiment of the invention provides a method of operating a Galois field multiplier in a processor. An n bit multiplier and an n bit multiplicand are received during a first group of one or more clock cycles. An (2n−1) bit product is calculated based on the n bit multiplicand and the n bit multiplier. The (2n−1) bit product is stored in a first memory element during the first group of one or more clock cycles. An n bit polynomial value is received during a second group of one or more clock cycles. During the second group of one or more clock cycles, the (2n−1) bit product is divided by the n bit polynomial value producing an n bit result. The n bit result is stored in a second memory element during the second group of one or more clock cycles.
摘要翻译：本发明的实施例提供了一种在处理器中操作伽罗瓦域乘法器的方法。在一个或多个时钟周期的第一组期间接收n位乘法器和n位被乘数。基于n位被乘数和n位乘法器计算（2n-1）位乘积。（2n-1）位产品在一个或多个时钟周期的第一组期间被存储在第一存储器元件中。在一个或多个时钟周期的第二组期间接收n位多项式值。在一个或多个时钟周期的第二组期间，（2n-1）位乘积除以产生n位结果的n位多项式值。在一个或多个时钟周期的第二组期间，n位结果存储在第二存储器元件中。

3. 发明申请

US20130179484A1 Efficient Technique for Optimal Re-Use of Hardware In the Implementation of Instructions Used in Viterbi, Turbo and LPDC Decoders 有权
标题翻译：在维特比，Turbo和LPDC解码器中使用的指令的实现中，最佳重用硬件的高效技术
公开(公告)号：US20130179484A1
公开(公告)日：2013-07-11
申请号：US12874699
申请日：2010-09-02
申请人： Shriram D. Moharil , Timothy D. Anderson
发明人： Shriram D. Moharil , Timothy D. Anderson
IPC分类号： G06F7/575
CPC分类号： G06F7/575 , G06F7/544
摘要： Low density parity check (LDPC) decoding can be mapped to a class of DSP instructions called MINST. The MINST class of instructions significantly enhance the efficiency of LDPC decoding by merging several of the functions required by LDPC decoders into a single MINST instruction. This invention is an efficient implementation of the MINST class of instructions using a configurable three input arithmetic logic unit. The carry output results of the three input arithmetic logic unit enable permit boundary decisions in a range determination required by the MINST instruction. The preferred embodiment employs 2's complement arithmetic and carry-save adder logic. This invention allows reuse of hardware required to implement MAX* functions in LDPC functions.
摘要翻译：低密度奇偶校验（LDPC）解码可以映射到称为MINST的一类DSP指令。 MINST类的指令通过将LDPC解码器所需的几个功能合并到单个MINST指令中，显着提高了LDPC解码的效率。本发明是使用可配置的三输入算术逻辑单元的MINST类指令的有效实现。三输入算术逻辑单元的进位输出结果在MINST指令要求的范围确定中允许允许边界判定。优选实施例采用2的补码运算和进位保存加法器逻辑。本发明允许重用在LDPC功能中实现MAX *功能所需的硬件。

4. 发明申请

US20120016919A1 EXTENDED-WIDTH SHIFTER FOR ARITHMETIC LOGIC UNIT 有权
标题翻译：用于算术逻辑单元的扩展宽度更新
公开(公告)号：US20120016919A1
公开(公告)日：2012-01-19
申请号：US13175938
申请日：2011-07-04
申请人： Timothy D. Anderson , Shriram D. Moharil
发明人： Timothy D. Anderson , Shriram D. Moharil
IPC分类号： G06F5/01
CPC分类号： G06F5/017
摘要： A processor includes a shift device for extending the width of a rotator without increasing propagation delays. An extended-width result is obtained by combining a rotation result with a shift result in accordance with a mask that is selected in response to at least a portion of the value of the degree to which a data word is to be shifted.
摘要翻译：处理器包括用于在不增加传播延迟的情况下延伸旋转器的宽度的移位装置。通过将旋转结果与移位结果组合，获得扩展宽度结果，该移位结果是根据数据字要被移位的程度的值的至少一部分而被选择的掩码。

5. 发明授权

US08650239B2 Hardware implementation of a Galois field multiplier 有权
标题翻译：伽罗瓦域乘法器的硬件实现
公开(公告)号：US08650239B2
公开(公告)日：2014-02-11
申请号：US12875732
申请日：2010-09-03
申请人： Shriram D. Moharil , Rejitha Nair
发明人： Shriram D. Moharil , Rejitha Nair
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： An embodiment of the invention provides a method of operating a Galois field multiplier in a processor. An n bit multiplier and an n bit multiplicand are received during a first group of one or more clock cycles. An (2n−1) bit product is calculated based on the n bit multiplicand and the n bit multiplier. The (2n−1) bit product is stored in a first memory element during the first group of one or more clock cycles. An n bit polynomial value is received during a second group of one or more clock cycles. During the second group of one or more clock cycles, the (2n−1) bit product is divided by the n bit polynomial value producing an n bit result. The n bit result is stored in a second memory element during the second group of one or more clock cycles.
摘要翻译：本发明的实施例提供了一种在处理器中操作伽罗瓦域乘法器的方法。在一个或多个时钟周期的第一组期间接收n位乘法器和n位被乘数。基于n位被乘数和n位乘法器计算（2n-1）位乘积。（2n-1）位产品在一个或多个时钟周期的第一组期间被存储在第一存储器元件中。在一个或多个时钟周期的第二组期间接收n位多项式值。在一个或多个时钟周期的第二组期间，（2n-1）位乘积除以产生n位结果的n位多项式值。在一个或多个时钟周期的第二组期间，n位结果存储在第二存储器元件中。

6. 发明授权

US08601040B2 Reduced-level shift overflow detection 有权
标题翻译：降级移位溢出检测
公开(公告)号：US08601040B2
公开(公告)日：2013-12-03
申请号：US12891718
申请日：2010-09-27
申请人： Timothy D. Anderson , Shriram D. Moharil
发明人： Timothy D. Anderson , Shriram D. Moharil
IPC分类号： G06F15/00
CPC分类号： G06F9/30032 , G06F9/30014
摘要： A processor includes a shift overflow detector for rapidly detecting overflows that may result during execution of a shift instruction. Shift indication signals are generated in response to changes in logic state between adjacent pairs of bits of a received shift data word. A received shift amount is decoded to produce decoded shift signals that indicate an amount of shifting for the received shift data word. An overflow condition is detected in response to the generated shift indication signals and the decoded shift signals and an indication of the detected overflow condition is provided.
摘要翻译：处理器包括用于快速检测在执行移位指令期间可能导致的溢出的移位溢出检测器。响应于接收到的移位数据字的相邻位之间的逻辑状态的变化而产生移位指示信号。接收到的移位量被解码以产生指示所接收的移位数据字的移位量的解码移位信号。响应于生成的移位指示信号和解码的移位信号检测溢出条件，并且提供检测到的溢出条件的指示。

7. 发明申请

US20130179483A1 Technique for Optimization and Re-Use of Hardware In the Implementation of Instructions Used in Viterbi and Turbo Decoding, Using Carry and Save Arithmetic 有权
标题翻译：在维特比和Turbo解码中使用的指令实现中优化和重用硬件的技术，使用进位和保存算术
公开(公告)号：US20130179483A1
公开(公告)日：2013-07-11
申请号：US12874653
申请日：2010-09-02
申请人： Timothy D. Anderson , Shriram D. Moharil
发明人： Timothy D. Anderson , Shriram D. Moharil
IPC分类号： G06F17/12
CPC分类号： G06F17/12 , H03M13/3922 , H03M13/395 , H03M13/4107 , H03M13/6502 , H03M13/6511 , H03M13/6586
摘要： The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2−b2+c2) with (x2+y2+z2); and (a3+b3−c3) with (x3+y3+z3); implementing an efficient method of computing (a4−b4−c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.
摘要翻译：本发明提供了一种用于在使用进位保存算术实现维特比和Turbo解码器中优化和重用硬件的手段。每个目标申请的成功规定要求面对两个主要问题。这些是：将求和项（a2-b2 + c2）与（x2 + y2 + z2）的计算合并; 和（a3 + b3-c3）与（x3 + y3 + z3）实现有效的计算方法（a4-b4-c4）; 并将该计算与（x4 + y4 + z4）合并。本发明解决了这两个问题，并且成功地将维特比指令与实现Turbo指令所需的硬件的完全重用相结合。通过有效地采用进位保存算法来优化两类指令所需的硬件。

8. 发明授权

US08880855B2 Dual register data path architecture with registers in a data file divided into groups and sub-groups 有权
标题翻译：双寄存器数据路径架构，将数据文件中的寄存器分为组和子组
公开(公告)号：US08880855B2
公开(公告)日：2014-11-04
申请号：US13233025
申请日：2011-09-15
申请人： Timothy D Anderson , Duc Quang Bui , Eric Biscondi , Shriram D Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
发明人： Timothy D Anderson , Duc Quang Bui , Eric Biscondi , Shriram D Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
IPC分类号： G06F9/34 , H03K21/00 , G06F1/32 , H03K19/00 , G06F7/483 , G06F12/02 , G06F9/30
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
摘要翻译：处理器包括第一和第二执行单元，每个执行单元被配置为在固定点操作数上执行第一类型的乘法指令，并且在浮点操作数上执行第二类型的乘法指令。处理器的寄存器文件将操作数存储在寄存器中，每个可操作数可由用于执行第一和第二类操作的指令来寻址。指令解码单元响应于第一类型的至少一个乘法指令和第二类型的至少一个乘法指令，同时使第一组寄存器和第一执行单元之间的第一数据路径和以使得能够在第二组寄存器和第二执行单元之间建立第二数据路径。

9. 发明申请

US20130275485A1 Technique for Optimization and Re-Use of Hardware in the Implementation of Instructions Used in Viterbi and Turbo Decoding, Using Carry Save Arithmetic 审中-公开
标题翻译：在维特比和Turbo解码中使用的指令实现中优化和重用硬件的技术，使用保存算法
公开(公告)号：US20130275485A1
公开(公告)日：2013-10-17
申请号：US13916810
申请日：2013-06-13
申请人： Timothy D. Anderson , Shriram D. Moharil
发明人： Timothy D. Anderson , Shriram D. Moharil
IPC分类号： G06F17/12
CPC分类号： G06F17/12 , H03M13/3922 , H03M13/395 , H03M13/4107 , H03M13/6502 , H03M13/6511 , H03M13/6586
摘要： The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2−b2+c2) with (x2+y2+z2); and (a3+b3−c3) with (x3+y3+z3); implementing an efficient method of computing (a4−b4−c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.
摘要翻译：本发明提供了一种用于在使用进位保存算术实现维特比和Turbo解码器中优化和重用硬件的手段。每个目标申请的成功规定要求面对两个主要问题。这些是：将求和项（a2-b2 + c2）与（x2 + y2 + z2）的计算合并; 和（a3 + b3-c3）与（x3 + y3 + z3）实现有效的计算方法（a4-b4-c4）; 并将该计算与（x4 + y4 + z4）合并。本发明解决了这两个问题，并且成功地将维特比指令与实现Turbo指令所需的硬件的完全重用相结合。通过有效地采用进位保存算法来优化两类指令所需的硬件。

10. 发明申请

US20120079247A1 DUAL REGISTER DATA PATH ARCHITECTURE 有权
标题翻译：双重注册数据路径架构
公开(公告)号：US20120079247A1
公开(公告)日：2012-03-29
申请号：US13233025
申请日：2011-09-15
申请人： Timothy D. Anderson , Duc Quang Bui , Eric Biscondi , Shriram D. Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
发明人： Timothy D. Anderson , Duc Quang Bui , Eric Biscondi , Shriram D. Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
IPC分类号： G06F9/30
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
摘要翻译：处理器包括第一和第二执行单元，每个执行单元被配置为在固定点操作数上执行第一类型的乘法指令，并且在浮点操作数上执行第二类型的乘法指令。处理器的寄存器文件将操作数存储在寄存器中，每个可操作数可由用于执行第一和第二类操作的指令来寻址。指令解码单元响应于第一类型的至少一个乘法指令和第二类型的至少一个乘法指令，同时使第一组寄存器和第一执行单元之间的第一数据路径和以使得能够在第二组寄存器和第二执行单元之间建立第二数据路径。

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