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1. 发明申请

US20130169332A1 Family of Multiplexer/Flip-Flops with Enhanced Testability 有权
标题翻译：具有增强可测性的多路复用器/触发器系列
公开(公告)号：US20130169332A1
公开(公告)日：2013-07-04
申请号：US12796949
申请日：2010-06-09
申请人： Mujibur Rahman , Timothy D. Anderson , Alan Hales
发明人： Mujibur Rahman , Timothy D. Anderson , Alan Hales
IPC分类号： H03K3/356
CPC分类号： H03K3/356 , H03K3/356052
摘要： A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.
摘要翻译：多位组合多路复用器和触发器电路具有多个位电路。每个位电路包括和输入部分，触发器部分和每位控制部分。输入部分具有用于多个输入信号和相应的输入传递门的输入。输入通过门的输出端连接到触发器部分的输入端。每个位控制部分包括用于每个输入端的反相器。存在组合控制部分，其接收时钟信号和用于仅选择一个输入信号的控制信号。组合控制部分包括组合时钟信号和选择信号的每个输入信号的逻辑“与”。每个逻辑AND的输出连接到每个位每个控制电路的相应反相器的输入端。输入通道门由对应的逻辑与和相应的反相器控制。

2. 发明授权

US08525565B2 Family of multiplexer/flip-flops with enhanced testability 有权
标题翻译：具有增强可测性的多路复用器/触发器系列
公开(公告)号：US08525565B2
公开(公告)日：2013-09-03
申请号：US12796949
申请日：2010-06-09
申请人： Mujibur Rahman , Timothy D. Anderson , Alan Hales
发明人： Mujibur Rahman , Timothy D. Anderson , Alan Hales
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356 , H03K3/356052
摘要： A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.
摘要翻译：多位组合多路复用器和触发器电路具有多个位电路。每个位电路包括和输入部分，触发器部分和每位控制部分。输入部分具有用于多个输入信号和相应的输入传递门的输入。输入通过门的输出端连接到触发器部分的输入端。每个位控制部分包括用于每个输入端的反相器。存在组合控制部分，其接收时钟信号和用于仅选择一个输入信号的控制信号。组合控制部分包括组合时钟信号和选择信号的每个输入信号的逻辑“与”。每个逻辑AND的输出连接到每个位每个控制电路的相应反相器的输入端。输入通道门由对应的逻辑与和相应的反相器控制。

3. 发明授权

US08397112B2 Test chain testability in a system for testing tri-state functionality 有权
标题翻译：用于测试三态功能的系统中的测试链可测性
公开(公告)号：US08397112B2
公开(公告)日：2013-03-12
申请号：US12969939
申请日：2010-12-16
申请人： Mujibur Rahman , Timothy Anderson , Alan Hales
发明人： Mujibur Rahman , Timothy Anderson , Alan Hales
IPC分类号： G01R31/28
CPC分类号： G01R31/31715
摘要： An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.
摘要翻译：本发明的实施例提供了一种用于检测测试链上的故障的系统。电路向测试链的输入端提供测试信号。测试链包括串联连接的多个缓冲器。寄存器接收表示测试链输出的逻辑值。寄存器将表示测试链的输出的逻辑值发送到测量电路，其中观察到该值。

4. 发明申请

US20130013656A1 THREE-TERM PREDICTIVE ADDER AND/OR SUBTRACTER 有权
标题翻译：三级预测添加剂和/或除草剂
公开(公告)号：US20130013656A1
公开(公告)日：2013-01-10
申请号：US13178508
申请日：2011-07-08
申请人： Timothy D. Anderson , Mujibur Rahman , Kai Chirca
发明人： Timothy D. Anderson , Mujibur Rahman , Kai Chirca
IPC分类号： G06F7/503
CPC分类号： G06F7/57 , G06F7/5055 , G06F7/506
摘要： A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.
摘要翻译：预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示纹波部分的位数在电位和。预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

5. 发明申请

US20120036408A1 Test Chain Testability In a System for Testing Tri-State Functionality 有权
标题翻译：用于测试三态功能的系统中的测试链可测试性
公开(公告)号：US20120036408A1
公开(公告)日：2012-02-09
申请号：US12969939
申请日：2010-12-16
申请人： Mujibur Rahman , Timothy Anderson , Alan Hales
发明人： Mujibur Rahman , Timothy Anderson , Alan Hales
IPC分类号： G06F11/27 , G01R31/28
CPC分类号： G01R31/31715
摘要： An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.
摘要翻译：本发明的实施例提供了一种用于检测测试链上的故障的系统。电路向测试链的输入端提供测试信号。测试链包括串联连接的多个缓冲器。寄存器接收表示测试链输出的逻辑值。寄存器将表示测试链的输出的逻辑值发送到测量电路，其中观察到该值。

6. 发明授权

US08918445B2 Circuit which performs split precision, signed/unsigned, fixed and floating point, real and complex multiplication 有权
标题翻译：执行分离精度，有符号/无符号，固定和浮点，实数和复数乘法的电路
公开(公告)号：US08918445B2
公开(公告)日：2014-12-23
申请号：US13239076
申请日：2011-09-21
申请人： Timothy David Anderson , Mujibur Rahman
发明人： Timothy David Anderson , Mujibur Rahman
IPC分类号： G06F7/44 , G06F13/366
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： An integrated multiplier circuit that operates on a variety of data formats including integer fixed point, signed or unsigned, real or complex, 8 bit, 16 bit or 32 bit as well as floating point data that may be single precision real, single precision complex or double precision. The circuit uses a single set of multiplier arrays to perform 16×16, 32×32 and 64×64 multiplies, 32×32 and 64×64 complex multiplies, 32×32 and 64×64 complex multiplies with one operand conjugated.
摘要翻译：集成乘法器电路，可对包括整数固定点，有符号或无符号，实数或复数，8位，16位或32位以及浮点数据在内的各种数据格式进行操作，这些数据可能是单精度实数，单精度复数或双精度。该电路使用单组乘法器阵列执行16×16,32×32和64×64乘法，32×32和64×64复乘，32×32和64×64复乘乘以一个操作数共轭。

7. 发明授权

US08880855B2 Dual register data path architecture with registers in a data file divided into groups and sub-groups 有权
标题翻译：双寄存器数据路径架构，将数据文件中的寄存器分为组和子组
公开(公告)号：US08880855B2
公开(公告)日：2014-11-04
申请号：US13233025
申请日：2011-09-15
申请人： Timothy D Anderson , Duc Quang Bui , Eric Biscondi , Shriram D Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
发明人： Timothy D Anderson , Duc Quang Bui , Eric Biscondi , Shriram D Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
IPC分类号： G06F9/34 , H03K21/00 , G06F1/32 , H03K19/00 , G06F7/483 , G06F12/02 , G06F9/30
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
摘要翻译：处理器包括第一和第二执行单元，每个执行单元被配置为在固定点操作数上执行第一类型的乘法指令，并且在浮点操作数上执行第二类型的乘法指令。处理器的寄存器文件将操作数存储在寄存器中，每个可操作数可由用于执行第一和第二类操作的指令来寻址。指令解码单元响应于第一类型的至少一个乘法指令和第二类型的至少一个乘法指令，同时使第一组寄存器和第一执行单元之间的第一数据路径和以使得能够在第二组寄存器和第二执行单元之间建立第二数据路径。

8. 发明授权

US08713086B2 Three-term predictive adder and/or subtracter 有权
标题翻译：三项预测加法器和/或减法器
公开(公告)号：US08713086B2
公开(公告)日：2014-04-29
申请号：US13178508
申请日：2011-07-08
申请人： Timothy D. Anderson , Mujibur Rahman , Kai Chirca
发明人： Timothy D. Anderson , Mujibur Rahman , Kai Chirca
IPC分类号： G06F7/50
CPC分类号： G06F7/57 , G06F7/5055 , G06F7/506
摘要： A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.
摘要翻译：预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示纹波部分的位数在电位和。预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

9. 发明申请

US20120191767A1 Circuit which Performs Split Precision, Signed/Unsigned, Fixed and Floating Point, Real and Complex Multiplication 有权
标题翻译：执行分离精度，签名/无符号，固定和浮点，真实和复杂乘法的电路
公开(公告)号：US20120191767A1
公开(公告)日：2012-07-26
申请号：US13239076
申请日：2011-09-21
申请人： Timothy David Anderson , Mujibur Rahman
发明人： Timothy David Anderson , Mujibur Rahman
IPC分类号： G06F7/487
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： An integrated multiplier circuit that operates on a variety of data formats including integer fixed point, signed or unsigned, real or complex, 8 bit, 16 bit or 32 bit as well as floating point data that may be single precision real, single precision complex or double precision. The circuit uses a single set of multiplier arrays to perform 16×16, 32×32 and 64×64 multiplies, 32×32 and 64×64 complex multiplies, 32×32 and 64×64 complex multiplies with one operand conjugated.
摘要翻译：集成乘法器电路，可对包括整数固定点，有符号或无符号，实数或复数，8位，16位或32位以及浮点数据在内的各种数据格式进行操作，这些数据可能是单精度实数，单精度复数或双精度。该电路使用单组乘法器阵列执行16×16,32×32和64×64乘法，32×32和64×64复乘，32×32和64×64复乘乘以一个操作数共轭。

10. 发明申请

US20120079247A1 DUAL REGISTER DATA PATH ARCHITECTURE 有权
标题翻译：双重注册数据路径架构
公开(公告)号：US20120079247A1
公开(公告)日：2012-03-29
申请号：US13233025
申请日：2011-09-15
申请人： Timothy D. Anderson , Duc Quang Bui , Eric Biscondi , Shriram D. Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
发明人： Timothy D. Anderson , Duc Quang Bui , Eric Biscondi , Shriram D. Moharil , Mujibur Rahman , Soujanya Narnur , Peter Richard Dent , Ashish Rai Shrivastava
IPC分类号： G06F9/30
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
摘要翻译：处理器包括第一和第二执行单元，每个执行单元被配置为在固定点操作数上执行第一类型的乘法指令，并且在浮点操作数上执行第二类型的乘法指令。处理器的寄存器文件将操作数存储在寄存器中，每个可操作数可由用于执行第一和第二类操作的指令来寻址。指令解码单元响应于第一类型的至少一个乘法指令和第二类型的至少一个乘法指令，同时使第一组寄存器和第一执行单元之间的第一数据路径和以使得能够在第二组寄存器和第二执行单元之间建立第二数据路径。

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