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1. 发明授权

US08510699B1 Performance driven layout optimization using morphing of a basis set of representative layouts 失效
标题翻译：性能驱动布局优化使用变形的基础代表性布局
公开(公告)号：US08510699B1
公开(公告)日：2013-08-13
申请号：US13416588
申请日：2012-03-09
申请人： Emrah Acar , Aditya Bansal , Rama N. Singh , Amith Singhee
发明人： Emrah Acar , Aditya Bansal , Rama N. Singh , Amith Singhee
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F9/455 , G06F17/5068
摘要： Techniques for generating variants of a circuit layout and evaluating quality of the variants are provided. In one aspect, a method for generating at least one variant layout for a cell design includes the following steps. At least a first basis layout and a second basis layout are obtained for the cell design, each having a plurality of shapes, each of the shapes being a polygon having a plurality of sides and vertices. One or more of the shapes in the first basis layout are linked with one or more of the shapes in the second basis layout that represent a common feature of the cell design resulting in a plurality of linked shapes. Starting with either the first basis layout or the second basis layout, a location of the vertices of each of the linked shapes are changed to produce the variant layout for the cell design.
摘要翻译：提供了用于产生电路布局的变型和评估变体的质量的技术。一方面，用于为单元设计生成至少一个变体布局的方法包括以下步骤。为单元设计获得至少第一基础布局和第二基本布局，每个布局具有多个形状，每个形状是具有多个边和顶点的多边形。第一基本布局中的一个或多个形状与第二基本布局中的一个或多个形状相关联，其表示单元设计的共同特征，导致多个连接形状。从第一基本布局或第二基本布局开始，改变每个链接形状的顶点的位置，以产生单元格设计的变体布局。

2. 发明申请

US20130320340A1 CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS 有权
公开(公告)号：US20130320340A1
公开(公告)日：2013-12-05
申请号：US13488532
申请日：2012-06-05
申请人： Emrah Acar , Aditya Bansal , Dureseti Chidambarrao , Liang-Teck Pang , Amith Singhee
发明人： Emrah Acar , Aditya Bansal , Dureseti Chidambarrao , Liang-Teck Pang , Amith Singhee
IPC分类号： H01L21/66 , H01L23/50
CPC分类号： H01L22/34 , H01L22/14 , H01L27/0203 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

3. 发明授权

US08969104B2 Circuit technique to electrically characterize block mask shifts 有权
标题翻译：电路技术，用于表征块掩模移位
公开(公告)号：US08969104B2
公开(公告)日：2015-03-03
申请号：US13488532
申请日：2012-06-05
申请人： Emrah Acar , Aditya Bansal , Dureseti Chidambarrao , Liang-Teck Pang , Amith Singhee
发明人： Emrah Acar , Aditya Bansal , Dureseti Chidambarrao , Liang-Teck Pang , Amith Singhee
IPC分类号： H01L23/34
CPC分类号： H01L22/34 , H01L22/14 , H01L27/0203 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.
摘要翻译：物理测试集成电路具有对应于集成电路设计的多个重复电路部分。这些部分中的第一部分被制造成具有标称块掩模位置，并且附加的部分被有意地用块掩模位置与标称块掩模位置的预定逐渐增加的偏移来制造。对于每个部分，确定第一场效应晶体管和第二场效应晶体管之间的阈值电压差。块掩模位置的预定逐渐增加的偏移在从第一场效应晶体管到第二场效应晶体管的方向上。在与零差异的阈值电压的差的变化相对应的逐行增加偏移的值处确定块掩模覆盖公差。还公开了用于片上监视的方法和相应的电路。

4. 发明申请

US20110115463A1 DIFFERENTIAL FET STRUCTURES FOR ELECTRICAL MONITORING OF OVERLAY 失效
标题翻译：用于覆盖电气监测的差分FET结构
公开(公告)号：US20110115463A1
公开(公告)日：2011-05-19
申请号：US12617901
申请日：2009-11-13
申请人： Emrah Acar , Aditya Bansal , Amith Singhee
发明人： Emrah Acar , Aditya Bansal , Amith Singhee
IPC分类号： G01N27/00
CPC分类号： G03F7/70633 , H01L22/34
摘要： A method and apparatus for determining overlay includes an array of electronic devices having structures formed in a plurality of layers and such that a device on a first end of the array includes an offset from a position of a device on a second end of the array. A measurement device is configured to measure electrical characteristics of the devices in the array to determine a transition position between the electrical characteristics. A comparison device is configured to determine an overlay between the layers based on a device associated with the transition position.
摘要翻译：用于确定覆盖层的方法和装置包括具有形成在多个层中的结构的电子器件的阵列，并且使得阵列的第一端上的器件包括从阵列的第二端上的器件的位置的偏移。测量装置被配置为测量阵列中的装置的电特性以确定电特性之间的转变位置。比较设备被配置为基于与转换位置相关联的设备来确定层之间的覆盖。

5. 发明授权

US08409882B2 Differential FET structures for electrical monitoring of overlay 失效
标题翻译：用于覆盖层电气监控的差分FET结构
公开(公告)号：US08409882B2
公开(公告)日：2013-04-02
申请号：US12617901
申请日：2009-11-13
申请人： Emrah Acar , Aditya Bansal , Amith Singhee
发明人： Emrah Acar , Aditya Bansal , Amith Singhee
IPC分类号： H01L21/66
CPC分类号： G03F7/70633 , H01L22/34
摘要： A method and apparatus for determining overlay includes an array of electronic devices having structures formed in a plurality of layers and such that a device on a first end of the array includes an offset from a position of a device on a second end of the array. A measurement device is configured to measure electrical characteristics of the devices in the array to determine a transition position between the electrical characteristics. A comparison device is configured to determine an overlay between the layers based on a device associated with the transition position.
摘要翻译：用于确定覆盖层的方法和装置包括具有形成在多个层中的结构的电子器件的阵列，并且使得阵列的第一端上的器件包括从阵列的第二端上的器件的位置的偏移。测量装置被配置为测量阵列中的装置的电特性以确定电特性之间的转变位置。比较设备被配置为基于与转换位置相关联的设备来确定层之间的覆盖。

6. 发明授权

US08635483B2 Dynamically tune power proxy architectures 有权
标题翻译：动态调优电源代理架构
公开(公告)号：US08635483B2
公开(公告)日：2014-01-21
申请号：US13079842
申请日：2011-04-05
申请人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
发明人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
IPC分类号： G06F1/00 , G06F1/26 , G06F15/00 , G01R21/00 , G01R19/00
CPC分类号： G06F1/3243 , Y02D10/152
摘要： A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.
摘要翻译：提供了一种自动调整电源代理架构的机制。基于与在微处理器核心上执行的应用有关的条件集合，识别用于针对微处理器核心的一组活动中的每个活动的权重因子，从而形成一组权重因子。使用一组活动和一组权重因子生成用电量估计值。确定功率使用估计值是否大于识别微处理器核的最大功率使用的功率代理阈值。响应于功率使用估计值大于功率代理阈值，一组信号被发送到与微处理器核心相关联的功率代理单元中的一个或多个片上致动器，以及与组件相关联的一组操作参数被调整。

7. 发明授权

US06842714B1 Method for determining the leakage power for an integrated circuit 失效
标题翻译：确定集成电路漏电功率的方法
公开(公告)号：US06842714B1
公开(公告)日：2005-01-11
申请号：US10646426
申请日：2003-08-22
申请人： Emrah Acar , Anirudh Devgan , Ying Liu , Sani R. Nassif , Haihua Su
发明人： Emrah Acar , Anirudh Devgan , Ying Liu , Sani R. Nassif , Haihua Su
IPC分类号： G01R31/30 , G01R21/00 , G06F15/00 , G06F19/00
CPC分类号： G01R31/3004 , G01R31/3008
摘要： A method for determining full chip leakage power first estimates leakage power and dynamic power for each circuit macro. The power supply voltage to each macro is first assumed to be nominal. The power dissipation for each macro is modeled as a current source whose value is the estimated power divided by the nominal power supply voltage. The power distribution network is modeled as a resistive grids. The thermal environment of the IC and its electronic package are modeled as multi dimensional grids of thermal elements. Algebraic multi-grid (AMG) methods are used to calculate updated circuit macro voltages and temperatures. The macro voltages and temperatures are updated and updated leakage and dynamic power dissipation are calculated. Iterations are continued until leakage power converges to a final value.
摘要翻译：用于确定全芯片泄漏功率的方法首先估计每个电路宏的泄漏功率和动态功率。首先假设每个宏的电源电压为标称值。每个宏的功耗被建模为电流源，其值是估计功率除以标称电源电压。配电网被建模为电阻网格。 IC及其电子封装的热环境被模拟为热元件的多维栅格。代数多网格（AMG）方法用于计算更新的电路宏观电压和温度。更新宏电压和温度，并计算泄漏和动态功耗。直到泄漏功率收敛到最终值为止，继续进行迭代。

8. 发明授权

US08594989B2 Compensating for variations in device characteristics in integrated circuit simulation 失效
标题翻译：补偿集成电路仿真中器件特性的变化
公开(公告)号：US08594989B2
公开(公告)日：2013-11-26
申请号：US12420910
申请日：2009-04-09
申请人： Emrah Acar , Kanak B. Agarwal , Damir Jamsek , Sani R. Nassif
发明人： Emrah Acar , Kanak B. Agarwal , Damir Jamsek , Sani R. Nassif
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5036
摘要： According to a method of simulation data processing, a difference is determined between a simulated value of a characteristic for a simulated integrated circuit device and a corresponding empirical value of the characteristic for a fabricated integrated circuit device. A data structure containing a simulation model of the fabricated integrated circuit device is accessed, where the data structure includes a plurality of entries each accessed via a unique index and an index used to access the data structure is offset in accordance with the difference between the simulated value and the empirical value. Operation of the simulated integrated circuit device is then simulated utilizing a value obtained from one of the plurality of entries of the data structure. Results of the simulation are stored in a data storage medium.
摘要翻译：根据模拟数据处理的方法，在仿真集成电路器件的特性的模拟值与制造的集成电路器件的特性的对应经验值之间确定差异。访问包含制造的集成电路器件的仿真模型的数据结构，其中数据结构包括通过唯一索引访问的多个条目，并且用于访问数据结构的索引根据模拟的价值和经验价值。然后使用从数据结构的多个条目之一获得的值来模拟仿真集成电路器件的操作。模拟结果存储在数据存储介质中。

9. 发明申请

US20120260117A1 Dynamically Tune Power Proxy Architectures 有权
标题翻译：动态调谐电源代理架构
公开(公告)号：US20120260117A1
公开(公告)日：2012-10-11
申请号：US13079842
申请日：2011-04-05
申请人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
发明人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
IPC分类号： G06F1/28
CPC分类号： G06F1/3243 , Y02D10/152
摘要： A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.
摘要翻译：提供了一种自动调整电源代理架构的机制。基于与在微处理器核心上执行的应用有关的一组条件，识别用于针对微处理器核心的一组活动中的每个活动的权重因子，从而形成一组权重因子。使用一组活动和一组权重因子生成用电量估计值。确定功率使用估计值是否大于识别微处理器核的最大功率使用的功率代理阈值。响应于功率使用估计值大于功率代理阈值，一组信号被发送到与微处理器核心相关联的功率代理单元中的一个或多个片上致动器，以及与该组件相关联的一组操作参数被调整。

10. 发明申请

US20100262412A1 INTEGRATED CIRCUIT MODELING BASED ON EMPIRICAL TEST DATA 有权
标题翻译：基于实际测试数据的集成电路建模
公开(公告)号：US20100262412A1
公开(公告)日：2010-10-14
申请号：US12420891
申请日：2009-04-09
申请人： Emrah Acar , Kanak B. Agarwal , Damir Jamsek , Sani R. Nassif
发明人： Emrah Acar , Kanak B. Agarwal , Damir Jamsek , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In accordance with one embodiment, a plurality of empirical measurements of a fabricated integrated circuit including a fabricated transistor having multiple terminals is received. The plurality of empirical measurements each include an empirical terminal current set and an empirical terminal voltage set for the terminals of the fabricated transistor. A mathematical simulation model of a simulated transistor is also received. Utilizing the mathematical simulation model, an intermediate data set is calculated by determining, for each of a plurality of different terminal voltage sets, a simulated terminal current set and a simulated terminal charge set. A modeling tool processes the intermediate data set to obtain a time domain simulation model of the fabricated transistor that, for each of the plurality of empirical measurements, provides a simulated terminal charge set. The time domain simulation model is stored in a computer-readable data storage medium.
摘要翻译：根据一个实施例，接收包括具有多个端子的制造晶体管的制造的集成电路的多个经验测量。多个经验测量每个包括经验终端电流集合和为制造的晶体管的端子设置的经验终端电压。还接收了模拟晶体管的数学模拟模型。利用数学模拟模型，通过针对多个不同终端电压组中的每一个确定模拟终端电流集合和模拟终端电荷组来计算中间数据集。建模工具处理中间数据集以获得制造的晶体管的时域仿真模型，对于多个经验测量中的每一个提供模拟终端电荷组。时域仿真模型存储在计算机可读数据存储介质中。

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