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1. 发明授权

US07827514B2 Efficient electromagnetic modeling of irregular metal planes 有权
标题翻译：不规则金属平面的高效电磁建模
公开(公告)号：US07827514B2
公开(公告)日：2010-11-02
申请号：US11849346
申请日：2007-09-03
申请人： Michael W. Beattie , Anirudh Devgan , Byron L. Krauter , Hui Zheng
发明人： Michael W. Beattie , Anirudh Devgan , Byron L. Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
摘要翻译：通过将表面划分成不等长且不对齐的矩形的网格，将电路节点位置分配给每个矩形的中心，以及基于中心电路节点位置计算电容和电感参数，来对不规则导电平面中的电磁体进行建模的方法。使用自动递归二分法实现矩形化。电容段被分配给每个电路节点并与对应的矩形重合。感应片段被分配在相邻的矩形对之间，其中感应片段的宽度被定义为相应的一对矩形的公共边界，并且感应片段的长度被定义为两个矩形的电路节点之间的正常距离。电路节点在矩形中心的放置显着减少了节点和节点的数量，并提供了一个更快而又全面的分析框架。

2. 发明授权

US07558136B2 Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability 有权
标题翻译：用于评估静态存储单元动态稳定性的内部非对称方法和电路
公开(公告)号：US07558136B2
公开(公告)日：2009-07-07
申请号：US11838341
申请日：2007-08-14
申请人： Rajiv V. Joshi , Qiuyi Ye , Anirudh Devgan
发明人： Rajiv V. Joshi , Qiuyi Ye , Anirudh Devgan
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/006 , G11C29/12005 , G11C29/24 , G11C2029/5002
摘要： A memory cell having an asymmetric connection for evaluating dynamic stability provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By operating the cell and observing changes in performance caused by the asymmetry, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each crosscoupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
摘要翻译：具有用于评估动态稳定性的不对称连接的存储器单元提供了一种用于提高存储器阵列的性能超过当前水平/产量的机制。通过操作电池并观察由不对称引起的性能变化，可以通过设计和操作环境研究SRAM单元的动态稳定性。可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。或者或组合地，可以改变单元的输出处的负载以影响电池的性能。可以在生产或测试晶片中制造具有至少一个测试单元的存储器阵列，并且可以探测存储器单元的内部节点以提供进一步的信息。

3. 发明申请

US20070300191A1 EFFICIENT ELECTROMAGNETIC MODELING OF IRREGULAR METAL PLANES 有权
标题翻译：非正式金属电厂的有效电磁建模
公开(公告)号：US20070300191A1
公开(公告)日：2007-12-27
申请号：US11849346
申请日：2007-09-03
申请人： Michael Beattie , Anirudh Devgan , Byron Krauter , Hui Zheng
发明人： Michael Beattie , Anirudh Devgan , Byron Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
摘要翻译：通过将表面划分成不等长且不对齐的矩形的网格，将电路节点位置分配给每个矩形的中心，以及基于中心电路节点位置计算电容和电感参数，来对不规则导电平面中的电磁体进行建模的方法。使用自动递归二分法实现矩形化。电容段被分配给每个电路节点并与相应的矩形重合。感应片段被分配在相邻的矩形对之间，其中感应片段的宽度被定义为相应的一对矩形的公共边界，并且感应片段的长度被定义为两个矩形的电路节点之间的正常距离。电路节点在矩形中心的放置显着减少了节点和节点的数量，并提供了一个更快而又全面的分析框架。

4. 发明申请

US20070086232A1 Ring oscillator row circuit for evaluating memory cell performance 有权
标题翻译：用于评估存储单元性能的环形振荡器行电路
公开(公告)号：US20070086232A1
公开(公告)日：2007-04-19
申请号：US11250019
申请日：2005-10-13
申请人： Rajiv Joshi , Qiuyi Ye , Yuen Chan , Anirudh Devgan
发明人： Rajiv Joshi , Qiuyi Ye , Yuen Chan , Anirudh Devgan
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C29/50012
摘要： A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
摘要翻译：用于评估存储单元性能的环形振荡器行电路在实际的存储器电路环境中提供电路延迟和性能测量。环形振荡器用一行存储器单元实现，并且具有连接到一个或多个位线以及与环形振荡器单元基本相同的其它存储器单元的输出。可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

5. 发明申请

US20070058448A1 Bitline variable methods and circuits for evaluating static memory cell dynamic stability 失效
公开(公告)号：US20070058448A1
公开(公告)日：2007-03-15
申请号：US11225571
申请日：2005-09-13
申请人： Rajiv Joshi , Qiuyi Ye , Anirudh Devgan
发明人： Rajiv Joshi , Qiuyi Ye , Anirudh Devgan
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C11/41 , G11C29/006 , G11C29/50 , G11C2029/1204 , G11C2029/5002
摘要： Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the changes in the bitline voltage, the dynamic stability of the SRAM cell can be studied over designs and operating environments. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. In addition, cell power supply voltages can be split and set to different levels in order to study the effect of cell asymmetry in combination with bitline pre-charge voltage differences.

6. 发明授权

US06434729B1 Two moment RC delay metric for performance optimization 失效
标题翻译：两个时间RC延迟度量用于性能优化
公开(公告)号：US06434729B1
公开(公告)日：2002-08-13
申请号：US09542442
申请日：2000-04-04
申请人： Charles Jay Alpert , Anirudh Devgan , Chandramouli V. Kashyap
发明人： Charles Jay Alpert , Anirudh Devgan , Chandramouli V. Kashyap
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/505
摘要： An efficient method for optimizing RC circuit design to reduce delay. The method comprises: calculating a first moment and a second moment of impulse response for an RC circuit; (2) computing a delay value for each node of the RC circuit utilizing the first and second moments by multiplying the natural logarithm of 2 with a division of the squared power of the first impulse moment by the square root of the second impulse moment; and (3) analyzing each node to determine if the delay at that node is at a desired optimization condition for optimizing the circuit response.
摘要翻译：一种用于优化RC电路设计以减少延迟的有效方法。该方法包括：计算RC电路的脉冲响应的第一时刻和第二时刻; （2）利用第一和第二力矩计算RC电路的每个节点的延迟值，所述第一和第二力矩乘以2的自然对数与第一冲动力矩的平方功率除以第二冲动力矩的平方根; 和（3）分析每个节点以确定该节点处的延迟是否处于用于优化电路响应的期望的优化条件。

7. 发明申请

US20080319717A1 EFFICIENT METHOD AND COMPUTER PROGRAM FOR MODELING AND IMPROVING STATIC MEMORY PERFORMANCE ACROSS PROCESS VARIATIONS AND ENVIRONMENTAL CONDITIONS 有权
标题翻译：有效的方法和计算机程序，用于建模和改进静态记忆性能的过程变化和环境条件
公开(公告)号：US20080319717A1
公开(公告)日：2008-12-25
申请号：US12199161
申请日：2008-08-27
申请人： Rajiv V. Joshi , Anirudh Devgan
发明人： Rajiv V. Joshi , Anirudh Devgan
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5045 , G06F2217/10
摘要： An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield. Multiple cell designs can be compared for performance, yield and sensitivity of performance variables to circuit parameters over particular environmental conditions in order to select the best cell design.
摘要翻译：一种有效的方法和计算机程序，用于建模和改进在过程变化和环境条件之间的记忆性能，为提高存储器阵列的性能提供了超出当前水平/产量的机制。对于多个存储器性能变量中的每一个执行电路参数子集的统计（蒙特卡罗）分析，然后确定每个性能变量对每个电路参数的灵敏度。然后根据敏感度调整存储器单元的存储单元设计参数和/或操作条件，从而提高存储器产量和/或性能。一旦达到性能水平，然后可以使用敏感度来改变性能变量的概率分布，以获得更高的产量。为了选择最佳的单元设计，可以将多个单元设计与性能变量的性能，产出和灵敏度进行比较，以便在特定的环境条件下对电路参数进行比较。

8. 发明申请

US20080094878A1 RING OSCILLATOR ROW CIRCUIT FOR EVALUATING MEMORY CELL PERFORMANCE 失效
标题翻译：用于评估存储器单元性能的振荡器振荡器电路
公开(公告)号：US20080094878A1
公开(公告)日：2008-04-24
申请号：US11963794
申请日：2007-12-22
申请人： Rajiv Joshi , Qiuyi Ye , Yuen Chan , Anirudh Devgan
发明人： Rajiv Joshi , Qiuyi Ye , Yuen Chan , Anirudh Devgan
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C29/50012
摘要： A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
摘要翻译：用于评估存储单元性能的环形振荡器行电路在实际的存储器电路环境中提供电路延迟和性能测量。环形振荡器用一行存储器单元实现，并且具有连接到一个或多个位线以及与环形振荡器单元基本相同的其它存储器单元的输出。可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

9. 发明申请

US20080052646A1 LITHOGRAPHY AWARE LEAKAGE ANALYSIS 有权
标题翻译： LITHOGRAPHY AWARE泄漏分析
公开(公告)号：US20080052646A1
公开(公告)日：2008-02-28
申请号：US11781043
申请日：2007-07-20
申请人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
发明人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5068 , G06F2217/12
摘要： A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
摘要翻译：执行泄漏分析的方法包括接收指定集成电路的信息。然后确定与集成电路相关联的形状的邻域。基于形状附近生成与集成电路相关联的泄漏信息。可以通过从内部形状确定第一单元的边界的第一组间距来确定形状的邻域。可以从第一单元的边界到第二单元的形状来确定第二组间隔。可以使用第一和第二组间隔来表征光刻工艺。

10. 发明授权

US07134103B2 Method, system, and product for verifying voltage drop across an entire integrated circuit package 失效
标题翻译：用于验证整个集成电路封装的电压降的方法，系统和产品
公开(公告)号：US07134103B2
公开(公告)日：2006-11-07
申请号：US10738708
申请日：2003-12-17
申请人： Michael Werner Beattie , Anirudh Devgan , Byron Lee Krauter , Hui Zheng
发明人： Michael Werner Beattie , Anirudh Devgan , Byron Lee Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/40
摘要： A method, system, and product are disclosed for determining a voltage drop across an entire integrated circuit package. A geometric description of the entire integrated circuit package is determined. The description is subdivided into non-uniform areas. A resistance of each one of the non-uniform areas is determined. A resistive netlist of the entire integrated circuit package is then determined by combining the resistance of each one of the non-uniform areas. The package is then simulated utilizing the netlist to determine the voltage drop across the entire integrated circuit package.
摘要翻译：公开了一种用于确定跨整个集成电路封装的电压降的方法，系统和产品。确定整个集成电路封装的几何描述。描述细分为非均匀区域。确定每个不均匀区域的电阻。然后通过组合每个非均匀区域的电阻来确定整个集成电路封装的电阻网表。然后使用网表模拟封装以确定整个集成电路封装的电压降。

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