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1. 发明授权

US4514893A Fabrication of FETs 失效
标题翻译： FET的制造
公开(公告)号：US4514893A
公开(公告)日：1985-05-07
申请号：US489708
申请日：1983-04-29
申请人： Eliezer Kinsbron , William T. Lynch , Thomas E. Smith
发明人： Eliezer Kinsbron , William T. Lynch , Thomas E. Smith
IPC分类号： H01L29/812 , H01L21/336 , H01L21/338 , H01L29/10 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66575 , H01L29/1033 , H01L29/1079 , H01L29/66537
摘要： A method of fabricating field effect transistors which includes control of threshold potential by an ion implantation limited to the active channel area. The active channel area is defined by a photoresist pattern. Ions are implanted into the exposed area in a concentration to achieve a desired threshold. Appropriate metals are deposited over the channel area to form a gate electrode. The photoresist is lifted off leaving the gate electrode in position over the channel area. If desired, a layer of polysilicon can be included prior to resist formation and later removed by an etchant which does not attack the gate electrode.
摘要翻译：制造场效应晶体管的方法，其包括通过限于有源沟道区的离子注入来控制阈值电位。活性通道区域由光致抗蚀剂图案限定。离子以浓度植入暴露区域以达到期望的阈值。在通道区域上沉积合适的金属以形成栅电极。剥离光致抗蚀剂，使栅电极位于通道区域的正上方。如果需要，可以在抗蚀剂形成之前包括多晶硅层，并且随后通过不侵蚀栅电极的蚀刻剂除去。

2. 发明授权

US4471524A Method for manufacturing an insulated gate field effect transistor device 失效
标题翻译：绝缘栅场效应晶体管器件的制造方法
公开(公告)号：US4471524A
公开(公告)日：1984-09-18
申请号：US564368
申请日：1983-12-23
申请人： Eliezer Kinsbron , William T. Lynch
发明人： Eliezer Kinsbron , William T. Lynch
IPC分类号： H01L21/225 , H01L21/28
CPC分类号： H01L21/225 , H01L21/28 , Y10S438/92
摘要： An overall method for manufacturing an IGFET device having extremely shallow source and drain regions and reduced gate to source and drain overlap capacitances is disclosed. For silicon MOS devices, the method also provides for the formation of metal silicide layers on polysilicon gate electrodes and interconnection paths and the source and drain regions in the same fabrication step. Source and drain regions are formed by oxidation of an arsenic doped polysilicon source layer formed to be in contact with areas in the silicon surface in which such regions are to be formed. The rate of oxidation of the source layer exceeds the rate at which arsenic diffuses in the silicon at the oxidation temperature. Owing to a high segregation coefficient of arsenic in silicon dioxide, nearly all of the arsenic in the source layer is driven into extremely shallow source and drain regions which acquire high surface concentrations.
摘要翻译：公开了一种用于制造具有极浅源极和漏极区域以及减小的栅极至源极和漏极重叠电容的IGFET器件的总体方法。对于硅MOS器件，该方法还提供了在同一制造步骤中在多晶硅栅极电极和互连路径以及源极和漏极区域上形成金属硅化物层的方法。源极和漏极区域通过形成为与要形成这些区域的硅表面中的区域形成的砷掺杂多晶硅源层的氧化形成。源层的氧化速率超过在氧化温度下砷扩散的速率。由于二氧化硅中砷的分离系数高，源层中几乎所有的砷都被驱动到获得高表面浓度的极浅的源极和漏极区域。

3. 发明授权

US4432132A Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features 失效
标题翻译：通过活性氧离子蚀刻形成侧壁氧化物层，以确定亚微米特征
公开(公告)号：US4432132A
公开(公告)日：1984-02-21
申请号：US328368
申请日：1981-12-07
申请人： Eliezer Kinsbron , William T. Lynch
发明人： Eliezer Kinsbron , William T. Lynch
IPC分类号： H01L29/78 , H01L21/033 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/316 , H01L21/3213 , H01L21/336 , H01L21/42 , H01L21/423 , C23C15/00
CPC分类号： H01L29/66643 , H01L21/033 , H01L21/28132 , H01L21/31116 , H01L21/31604 , H01L21/32136 , H01L21/32137 , H01L29/66575
摘要： This invention involves the defining of a submicron feature (21 or 93) in a structure, typically an insulated gate field effect transistor structure (30, 40, or 110). This feature is defined by a sidewall oxide protective masking layer (21 or 71) formed by reactive oxygen ion etching of the structure being built at a time when an exposed surface thereof in the vicinity of the sidewall contains atoms of a material--for example, silicon or aluminum--which combine with the oxygen ions to form the sidewall oxide layer.
摘要翻译：本发明涉及在通常为绝缘栅场效应晶体管结构（30,40或110）的结构中限定亚微米特征（21或93）。该特征由在其侧壁附近的暴露表面包含材料原子的时候构建的结构的活性氧离子蚀刻形成的侧壁氧化物保护掩模层（21或71）限定，例如，硅或铝 - 其与氧离子结合以形成侧壁氧化物层。

4. 发明授权

US5212112A Selective epitaxy of silicon in silicon dioxide apertures with suppression of unwanted formation of facets 失效
标题翻译：硅酮二氧化硅选择性外观与抑制形成面料的抑制
公开(公告)号：US5212112A
公开(公告)日：1993-05-18
申请号：US704749
申请日：1991-05-23
申请人： William T. Lynch
发明人： William T. Lynch
IPC分类号： H01L21/20 , H01L21/336 , H01L21/76 , H01L21/762 , H01L29/78
CPC分类号： H01L21/76294 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： In the prior art, selective epitaxial growth (SEG) of semiconductors, performed typically in rectangular windows penetrating through a masking layer located on a major surface of semiconductor substrate, suffers from unwanted facet formation at the corners of the windows--whereby the desirable planar area available for transistor fabrication is reduced. Such facet formation is suppressed--i.e., the area occupied by unwanted facets is reduced--by adding a relatively small lobe penetrating through the masking layer at each corner of each window prior to performing the SEG, whereby transistor packing density can be increased.

5. 发明授权

US4996576A Radiation-sensitive device 失效
标题翻译：辐射敏感设备
公开(公告)号：US4996576A
公开(公告)日：1991-02-26
申请号：US355053
申请日：1989-05-15
申请人： William T. Lynch , Lalita Manchanda
发明人： William T. Lynch , Lalita Manchanda
IPC分类号： H01L31/119
CPC分类号： H01L31/119
摘要： A p-channel depletion-mode MOS device is utilized for measuring low levels of ionizing radiation.
摘要翻译： p沟道耗尽型MOS器件用于测量低水平的电离辐射。

6. 发明授权

US4992394A Self aligned registration marks for integrated circuit fabrication 失效
标题翻译：用于集成电路制造的自对准对准标记
公开(公告)号：US4992394A
公开(公告)日：1991-02-12
申请号：US387721
申请日：1989-07-31
申请人： Robert L. Kostelak, Jr. , William T. Lynch , Sheila Vaidya
发明人： Robert L. Kostelak, Jr. , William T. Lynch , Sheila Vaidya
IPC分类号： H01L29/73 , H01L21/027 , H01L21/30 , H01L21/331 , H01L21/8249 , H01L23/544 , H01L27/06 , H01L29/732
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： In order to reduce alignment errors arising in the fabrication of semiconductor integrated circuits using electron beam lithography, enhanced registration marks--(i.e., registration marks that are more easily and accurately detectable by the electron beam)--are formed at the edges of oxide layers, located at the surface of a silicon body, by means of forming metal silicide layers having edges coincident with the edges of the oxide layers. Advantageously, the enhancing of the registgration marks by forming the metal silicide is performed subsequent to any high temperature processing steps, whereby the integrity of the marks is maintained.
摘要翻译：为了减少在使用电子束光刻的半导体集成电路的制造中产生的对准误差，在氧化物层的边缘处形成增强的对准标记（即，由电子束更容易和精确地检测的对准标记）通过形成具有与氧化物层的边缘重合的边缘的金属硅化物层，位于硅体的表面。有利的是，在任何高温处理步骤之后执行通过形成金属硅化物来增强注册标记，从而保持标记的完整性。

7. 发明授权

US5848187A Method and apparatus for entering and manipulating spreadsheet cell data 失效
公开(公告)号：US5848187A
公开(公告)日：1998-12-08
申请号：US486733
申请日：1995-06-07
申请人： Daniel Bricklin , William T. Lynch , John Friend
发明人： Daniel Bricklin , William T. Lynch , John Friend
IPC分类号： G06F17/21 , G06F17/24 , G06K9/22 , G06K9/62
CPC分类号： G06F17/246 , G06F17/211 , G06F17/24 , G06K9/00429
摘要： A method for entering and manipulating spreadsheet cell data is described. The present invention provides a method for determining the target cell for written information and for scaling the information to fit within the boundaries of the target cell. A multi-tiered character recognition scheme is used to improve the accuracy and speed of character recognition and translation of handwritten data. The original handwritten data is preserved so that either the translated data or original data may be displayed. The present invention also provides for improved editing of cell entries by allowing a plurality of editing tools to be selected. Manipulation of blocks of data can be accomplished with simple gestures. Arithmetic, statistical and logical functions can be invoked with a single command.

8. 发明授权

US5539214A Quantum bridges fabricated by selective etching of superlattice structures 失效
标题翻译：通过选择性蚀刻超晶格结构制造的量子桥
公开(公告)号：US5539214A
公开(公告)日：1996-07-23
申请号：US384166
申请日：1995-02-06
申请人： William T. Lynch , Kang L. Wang , Martin O. Tanner
发明人： William T. Lynch , Kang L. Wang , Martin O. Tanner
IPC分类号： H01L29/12 , H01L31/0352 , H01L33/04 , H01L33/06 , H01L29/06 , H01L31/0328
CPC分类号： H01L33/06 , B82Y10/00 , B82Y20/00 , H01L29/125 , H01L31/0352 , H01L31/035254 , H01L33/04
摘要： A quantum bridge structure including wires of a semiconductor material such as silicon which are formed by selectively etching a superlattice of alternating layers of at least two semiconductor materials. The quantum bridge is useful as a photo emission device, a photo detector device, and a chemical sensor. The wires exhibit improved electrical conduction properties due to decreased Coulomb scattering.
摘要翻译：包括通过选择性地蚀刻至少两种半导体材料的交替层的超晶格而形成的诸如硅的半导体材料的导线的量子桥结构。量子桥可用作光发射器件，光电检测器件和化学传感器。由于库仑散射减少，电线表现出改善的导电性能。

9. 发明授权

US5432366A P-I-N MOSFET for ULSI applications 失效
标题翻译： P-I-N MOSFET用于ULSI应用
公开(公告)号：US5432366A
公开(公告)日：1995-07-11
申请号：US70715
申请日：1993-05-28
申请人： Sanjay K. Banerjee , Suryanarayana Bhattacharya , William T. Lynch
发明人： Sanjay K. Banerjee , Suryanarayana Bhattacharya , William T. Lynch
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66477 , H01L29/1045 , H01L29/41783 , H01L29/66583 , H01L29/66537
摘要： A MOSFET device for ULSI circuits includes a semiconductor body having first and second spaced doped regions of a first conductivity type which function as source and drain regions, a third doped region between the first and second regions of a second conductivity type, and a first intrinsic region between the third doped region and the drain region, a channel of said MOSFET device including the third doped region and said first intrinsic region. Preferably the device further includes a second intrinsic region between the third doped region and the source region, the channel region of the MOSFET device including the third doped region, the first intrinsic region, and the second intrinsic region. The device further includes an insulating layer over the channel region and a gate electrode formed on the insulating layer over the channel region. A source electrode contact, the first doped region, and a drain electrode contact the second doped region. Several processes are described for fabricating the device.
摘要翻译：用于ULSI电路的MOSFET器件包括半导体本体，其具有第一和第二间隔的第一导电类型的掺杂区域，其作为源极和漏极区域，第二和第二导电类型的第一和第二区域之间的第三掺杂区域，所述第三掺杂区域和所述漏极区域之间的区域，所述MOSFET器件的沟道包括所述第三掺杂区域和所述第一本征区域。优选地，该器件还包括在第三掺杂区域和源极区域之间的第二本征区域，MOSFET器件的沟道区域包括第三掺杂区域，第一本征区域和第二本征区域。该器件还包括在沟道区上的绝缘层和形成在沟道区上的绝缘层上的栅电极。源电极接触，第一掺杂区和漏电极接触第二掺杂区。描述了用于制造装置的几个过程。

10. 发明授权

US5373180A Planar isolation technique for integrated circuits 失效
标题翻译：集成电路的平面隔离技术
公开(公告)号：US5373180A
公开(公告)日：1994-12-13
申请号：US121082
申请日：1993-09-14
申请人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda , Mark R. Pinto , Sheila Vaidya
发明人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda , Mark R. Pinto , Sheila Vaidya
IPC分类号： H01L29/73 , H01L21/331 , H01L21/76 , H01L21/762 , H01L21/763 , H01L29/78 , H01L27/04
CPC分类号： H01L21/76224 , H01L21/76205 , H01L21/763
摘要： Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.
摘要翻译：通过使用特定配置的埋入介质区域，具有严格设计规则（例如0.9微米及更小的设计规则）的器件被显着改进。特别地，集成电路中的凹陷介质区域，例如场氧化物，分离器件区域，或者具有围绕氧化物周围的埋入导电屏蔽层，或具有这样的结构，使得电介质的上表面不超过20 在形成器件有源区的硅的上表面下方。通过确保合适的配置，导致较慢操作的寄生电容显着降低，而漏电流保持在可接受的水平。

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