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1. 发明授权

US08095747B2 Memory system and method 有权
标题翻译：内存系统和方法
公开(公告)号：US08095747B2
公开(公告)日：2012-01-10
申请号：US12239532
申请日：2008-09-26
申请人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
发明人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
IPC分类号： G06F12/00
CPC分类号： G06F13/28
摘要： In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.
摘要翻译：在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控制器。配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

2. 发明申请

US20100082861A1 MEMORY SYSTEM AND METHOD 有权
标题翻译：记忆系统和方法
公开(公告)号：US20100082861A1
公开(公告)日：2010-04-01
申请号：US12239532
申请日：2008-09-26
申请人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
发明人： Bruce Barbara , Gabriel Li , Thinh Tran , Joseph Tzou
IPC分类号： G06F13/42 , G06F13/40 , G06F13/28
CPC分类号： G06F13/28
摘要： In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.
摘要翻译：在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控制器。配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

3. 发明授权

US07403446B1 Single late-write for standard synchronous SRAMs 有权
标题翻译：标准同步SRAM的单次后期写入
公开(公告)号：US07403446B1
公开(公告)日：2008-07-22
申请号：US11237378
申请日：2005-09-27
申请人： Suresh Parameswaran , Thinh Tran , Joseph Tzou
发明人： Suresh Parameswaran , Thinh Tran , Joseph Tzou
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/419 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C7/22 , G11C8/18
摘要： Synchronous SRAM may conform to Std. Sync or early-write at an external interface whilst providing late-write internally.
摘要翻译：同步SRAM可以符合标准在外部接口同步或提前写入，同时在内部提供后期写入。

4. 发明授权

US07269772B1 Method and apparatus for built-in self-test (BIST) of integrated circuit device 有权
标题翻译：内置自检（BIST）集成电路器件的方法和装置
公开(公告)号：US07269772B1
公开(公告)日：2007-09-11
申请号：US10785826
申请日：2004-02-23
申请人： Jun Li , Joseph Tzou , Thinh Tran
发明人： Jun Li , Joseph Tzou , Thinh Tran
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/31725
摘要： An integrated circuit device (200) can include a main portion (204) and a built-in self-test (BIST) portion (204) having outputs coupled to physical input structures (e.g., bond pads) (206) of the integrated circuit device (200). A BIST portion (202) can test timing critical parameters that take into account the effect of input structures (206). A BIST portion (202) can apply BIST test signals with a pipeline structure that can emulate timing parameters, such as a set-up time (Ts) and a clock-to-output time (Tco).
摘要翻译：集成电路装置（200）可以包括主要部分（204）和内置自检（BIST）部分（204），其具有耦合到集成电路的物理输入结构（例如，接合焊盘）（206）的输出装置（200）。 BIST部分（202）可以测试考虑到输入结构（206）的影响的时序关键参数。 BIST部分（202）可以应用具有可以模拟定时参数（诸如建立时间（Ts））和时钟到输出时间（Tco）的流水线结构的BIST测试信号。

5. 发明申请

US20120014202A1 MEMORY DEVICE AND METHOD 有权
标题翻译：存储器件和方法
公开(公告)号：US20120014202A1
公开(公告)日：2012-01-19
申请号：US13245856
申请日：2011-09-26
申请人： Joseph Tzou , Thinh Tran , Jun Li
发明人： Joseph Tzou , Thinh Tran , Jun Li
IPC分类号： G11C8/18
CPC分类号： G11C8/18 , G11C8/12
摘要： A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period
摘要翻译：在相同时间段中多次访问存储器件的方法可以包括在第一次访问顺序中，与第一时钟周期的第一部分同步地开始对多个存储体之一的访问操作，并开始访问与第一时钟周期的第二部分同步地操作到多个存储体中的另一个存储体，每个存储体具有单独的访问电路; 并且连续访问之间的时间比对于相同银行的背对背访问的访问速度更快; 其中在访问操作期间，在相同的时间段内访问每个存储体的存储位置

6. 发明授权

US07684257B1 Area efficient and fast static random access memory circuit and method 失效
标题翻译：区域高效快速静态随机存取电路及方法
公开(公告)号：US07684257B1
公开(公告)日：2010-03-23
申请号：US11958215
申请日：2007-12-17
申请人： Christopher Lee , Thinh Tran , Joseph Tzou , Morgan Whately
发明人： Christopher Lee , Thinh Tran , Joseph Tzou , Morgan Whately
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/1006 , G11C11/413
摘要： Disclosed is an accumulation memory circuit for providing a fast read, modify, and write operation in a single clock cycle time. The memory circuit is configured to read data stored in the memory device at an address. The memory circuit includes a reconfigurable adder unit generating read, accumulate and write output in a single clock cycle. The memory circuit is further configured to minimize data overflow. A high speed accumulation method comprises resetting a memory circuit; reading from an address of the memory circuit; performing internal addition within the memory circuit and rewriting into the address of the memory circuit in a single clock cycle.
摘要翻译：公开了一种用于在单个时钟周期时间内提供快速读取，修改和写入操作的累加存储器电路。存储器电路被配置为以地址读取存储在存储器件中的数据。存储器电路包括可重构加法器单元，其在单个时钟周期内产生读取，累加和写入输出。存储器电路还被配置为最小化数据溢出。高速累积方法包括：重置存储器电路; 从存储器电路的地址读取; 在存储器电路内执行内部加法，并在单个时钟周期内重写到存储器电路的地址。

7. 发明授权

US07196925B1 Memory array with current limiting device for preventing particle induced latch-up 有权
标题翻译：具有限流装置的存储器阵列，用于防止粒子诱发的闩锁
公开(公告)号：US07196925B1
公开(公告)日：2007-03-27
申请号：US10927583
申请日：2004-08-26
申请人： Joseph Tzou , Jithender Majjiga , Morgan Whately , Thinh Tran
发明人： Joseph Tzou , Jithender Majjiga , Morgan Whately , Thinh Tran
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A memory device can include a group of memory cells, which can be arranged in a column (100) that receives power by way of a first cell supply nodes (106-0 to 106-m). A current limiter (110) can be situated between first cell supply nodes (106-0 to 106-m) and a power supply (VH), and limit a current (llimit) to less than a latch-up holding current (lhold_lu) for the group of memory cells (100). In a particle event, such as an α-particle strike, a current limiter (110) can prevent a latch-up holding current (lhold_lu) from developing, thus preventing latch-up from occurring. Current limiter (110) can include p-channel transistors and/or resistors, and thus consume a relatively small area of the memory device.
摘要翻译：存储器设备可以包括一组存储器单元，其可以被布置在通过第一单元电源节点（106-0至106-m）接收电力的列（100）中。电流限制器（110）可以位于第一单元电源节点（106-0至106-m）和电源（VH）之间，并将电流（限制）限制为小于闭锁保持电流（lhold_lu）用于存储单元组（100）。在诸如α粒子撞击的粒子事件中，限流器（110）可以防止闩锁保持电流（lhold_lu）发展，从而防止发生闩锁。限流器（110）可以包括p沟道晶体管和/或电阻器，因此消耗存储器件的相对小的面积。

8. 发明授权

US07142477B1 Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses 有权
标题翻译：存储器接口系统和方法，用于使用单独的地址和数据总线减少连续读和写访问的周期时间
公开(公告)号：US07142477B1
公开(公告)日：2006-11-28
申请号：US10871825
申请日：2004-06-18
申请人： Thinh Tran , Joseph Tzou , Suresh Parameswaran
发明人： Thinh Tran , Joseph Tzou , Suresh Parameswaran
IPC分类号： G11C8/00
CPC分类号： G11C11/417 , G11C7/1066 , G11C8/18
摘要： A memory interface system and method are provided for transferring data between a memory controller and an array of storage elements. The storage elements are preferably SRAM elements, and the memory interface is preferably one having separate address bus paths and separate data bus paths. One address bus path is reserved for receiving read addresses and the other address bus path is reserved for receiving write addresses. One of the data bus paths is reserved for receiving read data from the array, and the other data bus path is reserved for receiving data written to the array. While bifurcating the address and data bus paths within the interface is transparent to the memory controller, the separate paths afford addressing phases of a read and write address operation to be partially overlapped, as well as the data transfer phases. This will essentially reduce the cycle time between a read and write memory access, and proves useful when maximizing the data throughput across the data bus when implementing double data rate (QDR) mechanisms.
摘要翻译：提供了一种用于在存储器控制器和存储元件阵列之间传送数据的存储器接口系统和方法。存储元件优选地是SRAM元件，并且存储器接口优选地具有分离的地址总线路径和单独的数据总线路径。保留一个地址总线路径用于接收读取地址，另一个地址总线路径被保留用于接收写入地址。数据总线路径之一被保留用于从阵列接收读取数据，另一条数据总线路径被保留用于接收写入阵列的数据。虽然分区接口内的地址和数据总线路径对于存储器控制器是透明的，但是单独的路径提供读取和写入地址操作的寻址阶段以部分重叠，以及数据传输阶段。这将实质上减少读写存储器访问之间的周期时间，并且在实现双数据速率（QDR）机制时在数据总线上最大化数据吞吐量时被证明是有用的。

9. 发明授权

US08149643B2 Memory device and method 有权
标题翻译：内存设备和方法
公开(公告)号：US08149643B2
公开(公告)日：2012-04-03
申请号：US12288984
申请日：2008-10-23
申请人： Joseph Tzou , Thinh Tran , Jun Li
发明人： Joseph Tzou , Thinh Tran , Jun Li
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C8/12
摘要： A memory device and method may include separating alternating read and write accesses to different banks of a memory device.
摘要翻译：存储器件和方法可以包括将交替的读和写访问分离到存储器件的不同组。

10. 发明申请

US20100103762A1 Memory device and method 有权
标题翻译：内存设备和方法
公开(公告)号：US20100103762A1
公开(公告)日：2010-04-29
申请号：US12288984
申请日：2008-10-23
申请人： Joseph Tzou , Thinh Tran , Jun Li
发明人： Joseph Tzou , Thinh Tran , Jun Li
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： G11C8/18 , G11C8/12
摘要： A memory device and method may include separating alternating read and write accesses to different banks of a memory device.
摘要翻译：存储器件和方法可以包括将交替的读和写访问分离到存储器件的不同组。

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