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1. 发明授权

US09449962B2 N-well/P-well strap structures 有权
标题翻译： N井/ P井带结构
公开(公告)号：US09449962B2
公开(公告)日：2016-09-20
申请号：US13814590
申请日：2011-08-04
申请人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
发明人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
IPC分类号： H01L27/04 , H01L21/8234 , H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/78
CPC分类号： H01L27/04 , H01L21/823493 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L29/7833
摘要： Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
摘要翻译：公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带来实现的较低要求。

2. 发明授权

US08217464B2 N-well/P-well strap structures 有权
标题翻译： N井/ P井带结构
公开(公告)号：US08217464B2
公开(公告)日：2012-07-10
申请号：US12851805
申请日：2010-08-06
申请人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
发明人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
IPC分类号： H01L29/78
CPC分类号： H01L21/823493 , H01L21/32055 , H01L21/76224 , H01L21/823475 , H01L21/823481 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L29/7833
摘要： Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
摘要翻译：公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带而获得较低的空间要求。

3. 发明申请

US20130140640A1 N-WELL/P-WELL STRAP STRUCTURES 审中-公开
标题翻译： N-WELL / P-WELL STRAP STRUCTURES
公开(公告)号：US20130140640A1
公开(公告)日：2013-06-06
申请号：US13814590
申请日：2011-08-04
申请人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin
发明人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin
IPC分类号： H01L27/04
CPC分类号： H01L27/04 , H01L21/823493 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L29/7833
摘要： Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
摘要翻译：公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带来实现的较低要求。

4. 发明授权

US06859065B2 Use of dangling partial lines for interfacing in a PLD 失效
标题翻译：使用悬挂的部分线路在PLD中进行接口
公开(公告)号：US06859065B2
公开(公告)日：2005-02-22
申请号：US10650465
申请日：2003-08-27
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736
摘要： A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.
摘要翻译： PLD中的路由结构以交错方式实现。否则将在路由架构边界“部分”和悬挂的路由线被驱动，为从边界向PLD核心路由信号提供了额外的灵活性。

5. 发明授权

US06653862B2 Use of dangling partial lines for interfacing in a PLD 有权
公开(公告)号：US06653862B2
公开(公告)日：2003-11-25
申请号：US10140911
申请日：2002-05-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
IPC分类号： H03K19177
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736
摘要： A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.

6. 发明授权

US08797790B1 Memory elements with soft error upset immunity 有权
标题翻译：内存元件具有软错误的不安定性
公开(公告)号：US08797790B1
公开(公告)日：2014-08-05
申请号：US12568638
申请日：2009-09-28
申请人： Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , William Bradley Vest
发明人： Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , William Bradley Vest
IPC分类号： G11C11/00 , G11C11/412 , G11C8/16
CPC分类号： G11C11/412 , G11C5/005 , G11C5/06 , G11C8/16 , G11C11/4125
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.
摘要翻译：提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。每个存储元件可以各自具有形成双稳态元件，一对地址晶体管和连接在两个逆变器之间的一对相对较弱的晶体管的四个逆变器状晶体管对，其形成公共输出节点，其抵抗快速变化它的状态。晶体管可以以形成双稳态存储器元件的图案连接，该双稳态存储器元件由于辐射打击而抵抗软错误不正常事件。可以使用地址晶体管对将数据加载到存储器元件中并从存储器元件读出。

7. 发明授权

US08716809B2 Hardened programmable devices 有权
标题翻译：硬化可编程器件
公开(公告)号：US08716809B2
公开(公告)日：2014-05-06
申请号：US13338701
申请日：2011-12-28
申请人： Andy L. Lee , Jeffrey T. Watt
发明人： Andy L. Lee , Jeffrey T. Watt
IPC分类号： H01L21/70
CPC分类号： H03K19/173 , G11C5/005 , H01L27/0207 , H03K19/1736 , H03K19/17784
摘要： Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.
摘要翻译：硬化可编程逻辑器件提供有可编程电路。可编程电路可以是硬连线的，以实现定制逻辑电路。可以使用通用制造掩模来形成可编程电路，并且可以用于制造硬化的可编程逻辑器件的产品系列，每一个可以实现不同的定制逻辑电路。可以使用定制制造掩模来硬编程电路来实现特定的定制逻辑电路。可编程电路可以是硬连线的，使得实现定制逻辑电路的硬化可编程逻辑器件的信号定时特性可以匹配使用配置数据实现相同定制逻辑电路的可编程逻辑器件的信号定时特性。

8. 发明授权

US08593195B1 High performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US08593195B1
公开(公告)日：2013-11-26
申请号：US13614526
申请日：2012-09-13
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03H11/16
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

9. 发明授权

US08502558B1 Computer-aided design tools and memory element power supply circuitry for selectively overdriving circuit blocks 有权
标题翻译：计算机辅助设计工具和存储元件电源电路，用于选择性地过驱动电路块
公开(公告)号：US08502558B1
公开(公告)日：2013-08-06
申请号：US13281135
申请日：2011-10-25
申请人： Irfan Rahim , Andy L. Lee
发明人： Irfan Rahim , Andy L. Lee
IPC分类号： G06F7/38 , H23K19/173
CPC分类号： H03K19/17784
摘要： Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different adjustable power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level. Memory elements associated with circuit blocks that contain critical paths can be overdriven at voltages that are larger than memory elements associated with circuit blocks that contain noncritical paths.
摘要翻译：集成电路提供有诸如多路复用器的电路，其可以被选择性地配置为将不同的可调电源电压路由到集成电路上的不同电路块。电路块可以包含由电源电压供电的存储器元件，并且以由电源电压确定的量值提供对应的静态输出控制信号。来自存储元件的控制信号可以被施加到电路块中的晶体管的栅极。集成电路上的逻辑可以在给定的电源电压电平下供电。存储元件可以以相对于给定电源电压电平升高的过驱动电压电平提供其输出信号。与包含关键路径的电路块相关联的存储器元件可以在大于与包含非关键路径的电路块相关联的存储器元件的电压上被过载。

10. 发明授权

US08461869B1 Apparatus for configuring performance of field programmable gate arrays and associated methods 有权
标题翻译：用于配置现场可编程门阵列性能和相关方法的装置
公开(公告)号：US08461869B1
公开(公告)日：2013-06-11
申请号：US13214147
申请日：2011-08-19
申请人： Irfan Rahim , Andy L. Lee , Bruce B. Pedersen , Jeffrey T. Watt , Mao Du , Richard G. Cliff
发明人： Irfan Rahim , Andy L. Lee , Bruce B. Pedersen , Jeffrey T. Watt , Mao Du , Richard G. Cliff
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K19/17784
摘要： An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.
摘要翻译：一种装置包括温度传感器，电压调节器和现场可编程门阵列（FPGA）。温度传感器和电压调节器分别适于提供温度信号，并提供至少一个输出电压。 FPGA包括适于接收电压调节器的至少一个输出电压的至少一个电路，以及适于提供至少一个电路的过程和温度指示的一组监视器电路。 FPGA还包括控制器，其适于从温度信号，从至少一个电路的处理和温度指示以及电压的至少一个输出电压导出体偏置信号和电压电平信号调节器所述控制器还适于将所述体偏置信号提供给所述至少一个电路中的至少一个晶体管，并且向所述电压调节器提供所述电压电平信号。

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