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1. 发明授权

US08217464B2 N-well/P-well strap structures 有权
标题翻译： N井/ P井带结构
公开(公告)号：US08217464B2
公开(公告)日：2012-07-10
申请号：US12851805
申请日：2010-08-06
申请人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
发明人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
IPC分类号： H01L29/78
CPC分类号： H01L21/823493 , H01L21/32055 , H01L21/76224 , H01L21/823475 , H01L21/823481 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L29/7833
摘要： Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
摘要翻译：公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带而获得较低的空间要求。

2. 发明授权

US09449962B2 N-well/P-well strap structures 有权
标题翻译： N井/ P井带结构
公开(公告)号：US09449962B2
公开(公告)日：2016-09-20
申请号：US13814590
申请日：2011-08-04
申请人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
发明人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
IPC分类号： H01L27/04 , H01L21/8234 , H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/78
CPC分类号： H01L27/04 , H01L21/823493 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L29/7833
摘要： Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
摘要翻译：公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带来实现的较低要求。

3. 发明申请

US20130140640A1 N-WELL/P-WELL STRAP STRUCTURES 审中-公开
标题翻译： N-WELL / P-WELL STRAP STRUCTURES
公开(公告)号：US20130140640A1
公开(公告)日：2013-06-06
申请号：US13814590
申请日：2011-08-04
申请人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin
发明人： Dustin Do , Andy L. Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin
IPC分类号： H01L27/04
CPC分类号： H01L27/04 , H01L21/823493 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L29/7833
摘要： Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
摘要翻译：公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带来实现的较低要求。

4. 发明申请

US20120032276A1 N-WELL/P-WELL STRAP STRUCTURES 有权
标题翻译： N-WELL / P-WELL STRAP STRUCTURES
公开(公告)号：US20120032276A1
公开(公告)日：2012-02-09
申请号：US12851805
申请日：2010-08-06
申请人： Dustin Do , Andy Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
发明人： Dustin Do , Andy Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L21/823493 , H01L21/32055 , H01L21/76224 , H01L21/823475 , H01L21/823481 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L29/7833
摘要： Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
摘要翻译：公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带而获得较低的空间要求。

5. 发明申请

US20120261738A1 N-Well/P-Well Strap Structures 审中-公开
标题翻译： N井/ P井带结构
公开(公告)号：US20120261738A1
公开(公告)日：2012-10-18
申请号：US13538438
申请日：2012-06-29
申请人： Dustin Do , Andy Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
发明人： Dustin Do , Andy Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
IPC分类号： H01L29/788
CPC分类号： H01L27/0207 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878
摘要： Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
摘要翻译：公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带而获得较低的空间要求。

6. 发明授权

US09196749B1 Programmable device with a metal oxide semiconductor field effect transistor 有权
标题翻译：具有金属氧化物半导体场效应晶体管的可编程器件
公开(公告)号：US09196749B1
公开(公告)日：2015-11-24
申请号：US13341310
申请日：2011-12-30
申请人： Charu Sardana , Albert Ratnakumar , Qi Xiang , Bradley Jensen
发明人： Charu Sardana , Albert Ratnakumar , Qi Xiang , Bradley Jensen
IPC分类号： H01L29/66 , H01L29/788 , H01L27/112
CPC分类号： H01L27/112 , H01L27/11206 , H01L29/66 , H01L29/7881
摘要： A programmable device with a metal oxide semiconductor field effect transistor (MOSFET) surrounded by a programmable substrate region is described. The MOSFET has a source and drain region separated by a channel region with an insulating region and gate disposed above the channel region. A junction disposed within the substrate region controls the programmable substrate region. Biasing the junction depletes the substrate region, which isolates the body of the MOSFET from a secondary well. When the junction is left unbiased, the body of the MOSFET is electrically coupled to the secondary well.
摘要翻译：描述了由可编程衬底区域包围的具有金属氧化物半导体场效应晶体管（MOSFET）的可编程器件。 MOSFET具有由具有绝缘区域的沟道区域和设置在沟道区域上方的栅极分隔的源极和漏极区域。设置在衬底区域内的接合部控制可编程衬底区域。偏置连接点会耗尽衬底区域，从而将MOSFET的主体与次级阱隔离。当结点保持不偏差时，MOSFET的主体电耦合到次级阱。

7. 发明申请

US20080071991A1 Using trap routines in a RISC microprocessor architecture 审中-公开
标题翻译：在RISC微处理器架构中使用陷阱程序
公开(公告)号：US20080071991A1
公开(公告)日：2008-03-20
申请号：US11981482
申请日：2007-10-31
申请人： George Shaw , Martin McClurg , Bradley Jensen , Russell Fish , Charles Moore
发明人： George Shaw , Martin McClurg , Bradley Jensen , Russell Fish , Charles Moore
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F9/30014 , G06F9/3005 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/322 , G06F9/3824 , G06F9/3861 , G06F9/3877 , G06F9/3879 , G09G5/363 , G09G5/393 , G09G2360/121 , G09G2360/126
摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.
摘要翻译：微处理器以100 MHz内部时钟频率执行100个本机MIPS峰值性能。中央处理单元（CPU）指令集是硬连线的，允许大多数指令在一个周期内执行。 “流通”设计允许下一条指令在先前指令完成之前启动，从而提高性能。微处理单元（MPU）包含52个通用寄存器，包括16个全局数据寄存器，一个索引寄存器，一个计数寄存器，一个16深可寻址寄存器/返回堆栈以及一个18深操作数堆栈。两个堆栈都包含顶部元素中的索引寄存器，缓存在芯片上，并在需要时自动溢出并从外部存储器中重新填充。堆栈最小化数据移动，并在过程调用，参数传递和变量赋值期间最小化存储器访问。此外，MPU还包含一个模式/状态寄存器和41个用于I / O，控制，配置和状态的本地寻址寄存器。 CPU包含高性能零操作数双堆栈架构MPU和执行指令传输数据，计数事件，测量时间和执行其他与时序相关的功能的输入输出处理器（IOP）。零操作数堆栈架构消除了操作数位。堆栈还可以在过程内和跨过程中最小化寄存器保存和加载，从而允许较短的指令序列和更快的运行代码。指令简单易于解码和执行，允许MPU和IOP在单个时钟周期内发出和完成指令，每个时钟周期为100个本机MIPS峰值执行。每次执行指令提取或预取时，CPU使用8位操作码，最多可从内存中获取四条指令。这些指令可以重复，而不会从内存重新读取。当直接连接到DRAM而没有高速缓存时，这将保持高性能。

8. 发明授权

US08878296B1 Electrostatic discharge protection circuitry 有权
标题翻译：静电放电保护电路
公开(公告)号：US08878296B1
公开(公告)日：2014-11-04
申请号：US12910416
申请日：2010-10-22
申请人： Bradley Jensen , Charles Y. Chu
发明人： Bradley Jensen , Charles Y. Chu
IPC分类号： H01L23/62
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits with electrostatic discharge (ESD) protection circuitry are provided. The ESD protection circuitry does not include polysilicon resistors. The ESD protection circuitry may include n-channel transistors coupled in parallel between an output node that is connected to an input/output pin and a ground terminal. The n-channel transistors may each have a drain terminal that is coupled to the output node through first metal paths and a source terminal that is coupled to the ground terminal through second metal paths. The first and second metal paths may be routed over gate terminals of the respective n-channel transistors to provide sufficient resistance. The first and second metal paths may provide desired pull-down resistance in the ESD protection circuitry so that the ESD protection circuitry can sink sufficient current through each of the n-channel transistors to protect internal circuitry from damage in an ESD event.
摘要翻译：提供具有静电放电（ESD）保护电路的集成电路。 ESD保护电路不包括多晶硅电阻。 ESD保护电路可以包括并联连接在连接到输入/输出引脚和接地端子的输出节点之间的n沟道晶体管。 n沟道晶体管可以各自具有通过第一金属路径耦合到输出节点的漏极端子和通过第二金属路径耦合到接地端子的源极端子。第一和第二金属路径可以在相应的n沟道晶体管的栅极端子上布线以提供足够的电阻。第一和第二金属路径可以在ESD保护电路中提供期望的下拉电阻，使得ESD保护电路可以吸收通过每个n沟道晶体管的足够电流，以保护内部电路免于ESD事件中的损坏。

9. 发明申请

US20120083094A1 INTEGRATED CIRCUIT GUARD RINGS 有权
标题翻译：集成电路保护环
公开(公告)号：US20120083094A1
公开(公告)日：2012-04-05
申请号：US13316241
申请日：2011-12-09
申请人： Bradley Jensen , Charles Y. Chu
发明人： Bradley Jensen , Charles Y. Chu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , H01L21/31053
摘要： Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.
摘要翻译：提供带保护环的集成电路。集成电路可以包括对外部噪声源敏感的内部电路。保护环可以围绕功能电路以将电路与噪声源隔离。保护环可以包括第一，第二和第三区域。第一和第三区域可以包括p阱。第二区域可以包括n阱。扩散区域的条纹可以形成在三个区域中的基板的表面。保护环中未被扩散区占据的区域被浅沟槽隔离（STI）结构所占据。虚设结构的条纹可以形成在相应的STI结构上，并且可能不与扩散区重叠。第一和第三区域中的扩散区域可被偏压到接地电压。第二部分中的扩散区域可以被偏置到正电源电压。

10. 发明授权

US08097925B2 Integrated circuit guard rings 有权
标题翻译：集成电路保护环
公开(公告)号：US08097925B2
公开(公告)日：2012-01-17
申请号：US12748300
申请日：2010-03-26
申请人： Bradley Jensen , Charles Y. Chu
发明人： Bradley Jensen , Charles Y. Chu
IPC分类号： H01L29/66 , H01L29/02
CPC分类号： H01L21/76229 , H01L21/31053
摘要： Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.
摘要翻译：提供带保护环的集成电路。集成电路可以包括对外部噪声源敏感的内部电路。保护环可以围绕功能电路以将电路与噪声源隔离。保护环可以包括第一，第二和第三区域。第一和第三区域可以包括p阱。第二区域可以包括n阱。扩散区域的条纹可以形成在三个区域中的基板的表面。保护环中未被扩散区占据的区域被浅沟槽隔离（STI）结构所占据。虚设结构的条纹可以形成在相应的STI结构上，并且可能不与扩散区重叠。第一和第三区域中的扩散区域可被偏压到接地电压。第二部分中的扩散区域可以被偏置到正电源电压。

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