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1. 发明授权

US08105885B1 Hardened programmable devices 有权
标题翻译：硬化可编程器件
公开(公告)号：US08105885B1
公开(公告)日：2012-01-31
申请号：US12852422
申请日：2010-08-06
申请人： Andy L. Lee , Jeffrey T. Watt
发明人： Andy L. Lee , Jeffrey T. Watt
IPC分类号： H01L21/82
CPC分类号： H03K19/173 , G11C5/005 , H01L27/0207 , H03K19/1736 , H03K19/17784
摘要： Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.
摘要翻译：硬化可编程逻辑器件提供有可编程电路。可编程电路可以是硬连线的，以实现定制逻辑电路。可以使用通用制造掩模来形成可编程电路，并且可以用于制造硬化的可编程逻辑器件的产品系列，每一个可以实现不同的定制逻辑电路。可以使用定制制造掩模来硬编程电路来实现特定的定制逻辑电路。可编程电路可以是硬连线的，使得实现定制逻辑电路的硬化可编程逻辑器件的信号定时特性可以匹配使用配置数据实现相同定制逻辑电路的可编程逻辑器件的信号定时特性。

2. 发明授权

US08289755B1 Volatile memory elements with soft error upset immunity 有权
标题翻译：易失性记忆元件，具有柔软的错误不耐受性
公开(公告)号：US08289755B1
公开(公告)日：2012-10-16
申请号：US12571346
申请日：2009-09-30
申请人： Irfan Rahim , Jeffrey T. Watt , Andy L. Lee , Myron Wai Wong , William Bradley Vest
发明人： Irfan Rahim , Jeffrey T. Watt , Andy L. Lee , Myron Wai Wong , William Bradley Vest
IPC分类号： G11C11/00
CPC分类号： G11C11/4125
摘要： Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.
摘要翻译：提供了显示对软错误扰乱的抗扰度的内存元素。存储器元件可以具有交叉耦合的反相器。可以使用可编程施密特触发器来实现逆变器。存储器元件可以通过向施密特触发器提供适当的电源电压来锁定和解锁。存储元件可以各自具有形成双稳态元件，至少一个地址晶体管和至少一个写使能晶体管的四个逆变器状晶体管对。写使能晶体管可以桥接四个节点中的两个。存储元件可以通过打开和关闭写使能晶体管来锁定和解锁。当存储器元件被解锁时，存储元件对状态变化的抵抗力较小，从而便于写操作。当存储器元件被锁定时，存储元件可以表现出对软错误扰动的增强的抗扰性。

3. 发明授权

US07800400B2 Configuration random access memory 有权
标题翻译：配置随机存取存储器
公开(公告)号：US07800400B2
公开(公告)日：2010-09-21
申请号：US11653001
申请日：2007-01-12
申请人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
发明人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。每个存储器元件具有存储该存储器元件的数据的电容器。一对交叉耦合的反相器连接到电容器。逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。每个配置随机存取存储器元件可以具有透明晶体管。电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。逆变器可以用升高的电源电压供电。

4. 发明授权

US08797790B1 Memory elements with soft error upset immunity 有权
标题翻译：内存元件具有软错误的不安定性
公开(公告)号：US08797790B1
公开(公告)日：2014-08-05
申请号：US12568638
申请日：2009-09-28
申请人： Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , William Bradley Vest
发明人： Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , William Bradley Vest
IPC分类号： G11C11/00 , G11C11/412 , G11C8/16
CPC分类号： G11C11/412 , G11C5/005 , G11C5/06 , G11C8/16 , G11C11/4125
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.
摘要翻译：提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。每个存储元件可以各自具有形成双稳态元件，一对地址晶体管和连接在两个逆变器之间的一对相对较弱的晶体管的四个逆变器状晶体管对，其形成公共输出节点，其抵抗快速变化它的状态。晶体管可以以形成双稳态存储器元件的图案连接，该双稳态存储器元件由于辐射打击而抵抗软错误不正常事件。可以使用地址晶体管对将数据加载到存储器元件中并从存储器元件读出。

5. 发明授权

US08716809B2 Hardened programmable devices 有权
标题翻译：硬化可编程器件
公开(公告)号：US08716809B2
公开(公告)日：2014-05-06
申请号：US13338701
申请日：2011-12-28
申请人： Andy L. Lee , Jeffrey T. Watt
发明人： Andy L. Lee , Jeffrey T. Watt
IPC分类号： H01L21/70
CPC分类号： H03K19/173 , G11C5/005 , H01L27/0207 , H03K19/1736 , H03K19/17784
摘要： Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.
摘要翻译：硬化可编程逻辑器件提供有可编程电路。可编程电路可以是硬连线的，以实现定制逻辑电路。可以使用通用制造掩模来形成可编程电路，并且可以用于制造硬化的可编程逻辑器件的产品系列，每一个可以实现不同的定制逻辑电路。可以使用定制制造掩模来硬编程电路来实现特定的定制逻辑电路。可编程电路可以是硬连线的，使得实现定制逻辑电路的硬化可编程逻辑器件的信号定时特性可以匹配使用配置数据实现相同定制逻辑电路的可编程逻辑器件的信号定时特性。

6. 发明授权

US08461869B1 Apparatus for configuring performance of field programmable gate arrays and associated methods 有权
标题翻译：用于配置现场可编程门阵列性能和相关方法的装置
公开(公告)号：US08461869B1
公开(公告)日：2013-06-11
申请号：US13214147
申请日：2011-08-19
申请人： Irfan Rahim , Andy L. Lee , Bruce B. Pedersen , Jeffrey T. Watt , Mao Du , Richard G. Cliff
发明人： Irfan Rahim , Andy L. Lee , Bruce B. Pedersen , Jeffrey T. Watt , Mao Du , Richard G. Cliff
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K19/17784
摘要： An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.
摘要翻译：一种装置包括温度传感器，电压调节器和现场可编程门阵列（FPGA）。温度传感器和电压调节器分别适于提供温度信号，并提供至少一个输出电压。 FPGA包括适于接收电压调节器的至少一个输出电压的至少一个电路，以及适于提供至少一个电路的过程和温度指示的一组监视器电路。 FPGA还包括控制器，其适于从温度信号，从至少一个电路的处理和温度指示以及电压的至少一个输出电压导出体偏置信号和电压电平信号调节器所述控制器还适于将所述体偏置信号提供给所述至少一个电路中的至少一个晶体管，并且向所述电压调节器提供所述电压电平信号。

7. 发明申请

US20120032702A1 HARDENED PROGRAMMABLE DEVICES 有权
标题翻译：硬化可编程器件
公开(公告)号：US20120032702A1
公开(公告)日：2012-02-09
申请号：US12852422
申请日：2010-08-06
申请人： Andy L. Lee , Jeffrey T. Watt
发明人： Andy L. Lee , Jeffrey T. Watt
IPC分类号： H03K19/0175 , G06F17/50 , H03K19/00 , H01L21/82
CPC分类号： H03K19/173 , G11C5/005 , H01L27/0207 , H03K19/1736 , H03K19/17784
摘要： Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.
摘要翻译：硬化可编程逻辑器件提供有可编程电路。可编程电路可以是硬连线的，以实现定制逻辑电路。可以使用通用制造掩模来形成可编程电路，并且可以用于制造硬化的可编程逻辑器件的产品系列，每一个可以实现不同的定制逻辑电路。可以使用定制制造掩模来硬编程电路来实现特定的定制逻辑电路。可编程电路可以是硬连线的，使得实现定制逻辑电路的硬化可编程逻辑器件的信号定时特性可以匹配使用配置数据实现相同定制逻辑电路的可编程逻辑器件的信号定时特性。

8. 发明申请

US20100321984A1 CONFIGURATION RANDOM ACCESS MEMORY 有权
标题翻译：配置随机存取存储器
公开(公告)号：US20100321984A1
公开(公告)日：2010-12-23
申请号：US12868575
申请日：2010-08-25
申请人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
发明人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
IPC分类号： G11C11/24
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。每个存储器元件具有存储该存储器元件的数据的电容器。一对交叉耦合的反相器连接到电容器。逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。每个配置随机存取存储器元件可以具有透明晶体管。电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。逆变器可以用升高的电源电压供电。

9. 发明授权

US08698516B2 Apparatus for improving performance of field programmable gate arrays and associated methods 有权
标题翻译：用于提高现场可编程门阵列性能的装置及相关方法
公开(公告)号：US08698516B2
公开(公告)日：2014-04-15
申请号：US13214144
申请日：2011-08-19
申请人： Irfan Rahim , Jeffrey T. Watt , Richard G. Cliff , Andy L. Lee , Ping-Chen Liu
发明人： Irfan Rahim , Jeffrey T. Watt , Richard G. Cliff , Andy L. Lee , Ping-Chen Liu
IPC分类号： H03K17/16
CPC分类号： H03K19/17784 , H03K19/17792
摘要： A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.
摘要翻译：现场可编程门阵列（FPGA）包括一组监视器电路，其适于为FPGA中的至少一个电路提供过程，电压和温度的指示，以及控制器，其适于导出所述at的至少一个电路的体偏值的范围用于至少一个电路的过程，电压和温度的指示的至少一个电路。 FPGA还包括体偏置发生器，其适于向至少一个电路中的至少一个晶体管提供体偏置信号。体偏置信号具有在体偏值范围内的值。

10. 发明授权

US08482963B1 Integrated circuits with asymmetric and stacked transistors 有权
标题翻译：具有不对称和堆叠晶体管的集成电路
公开(公告)号：US08482963B1
公开(公告)日：2013-07-09
申请号：US12629831
申请日：2009-12-02
申请人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
发明人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.
摘要翻译：不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。两个晶体管的栅极也连接在一起。两个晶体管可以具有不同的阈值电压。位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。不对称晶体管也可用于存储器单元中以减少泄漏。

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