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    • 1. 发明申请
    • METHODS OF FORMING GATE STRUCTURES FOR REDUCED LEAKAGE
    • 形成用于减少泄漏的门结构的方法
    • US20130157451A1
    • 2013-06-20
    • US13331055
    • 2011-12-20
    • Wuu-Cherng LinFangyun RichterChe Ta HsuWen Sun Wu
    • Wuu-Cherng LinFangyun RichterChe Ta HsuWen Sun Wu
    • H01L21/3205G06F17/50
    • G06F17/5081
    • Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
    • 提供了包含晶体管的集成电路。 晶体管可以包括形成在相关联的阱区上的栅极结构。 阱区可以被主动偏置并且可以用作身体终端。 一个晶体管的阱区可以邻近相邻晶体管的栅极结构形成。 如果相邻晶体管的栅极结构和一个晶体管的阱区都被主动偏置并且彼此靠近放置,则可能产生大量的泄漏。 可以使用计算机辅助设计工具来识别主动驱动的栅极端子和阱区域,并且可以用于确定每个栅极 - 阱对是否彼此间隔得足够远。 如果栅极阱对太靠近,则设计工具可以定位现有的栅极切割层并延伸现有的栅极切割层以切割主动驱动的栅极结构。
    • 5. 发明授权
    • Methods of forming gate structures for reduced leakage
    • 形成栅极结构以减少泄漏的方法
    • US08921217B2
    • 2014-12-30
    • US13331055
    • 2011-12-20
    • Wuu-Cherng LinFangyun RichterChe Ta HsuWen Sun Wu
    • Wuu-Cherng LinFangyun RichterChe Ta HsuWen Sun Wu
    • H01L21/3205H01L21/4763
    • G06F17/5081
    • Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
    • 提供了包含晶体管的集成电路。 晶体管可以包括形成在相关联的阱区上的栅极结构。 阱区可以被主动偏置并且可以用作身体终端。 一个晶体管的阱区可以邻近相邻晶体管的栅极结构形成。 如果相邻晶体管的栅极结构和一个晶体管的阱区都被主动偏置并且彼此靠近放置,则可能产生大量的泄漏。 可以使用计算机辅助设计工具来识别主动驱动的栅极端子和阱区域,并且可以用于确定每个栅极 - 阱对是否彼此间隔得足够远。 如果栅极阱对太靠近,则设计工具可以定位现有的栅极切割层并延伸现有的栅极切割层以切割主动驱动的栅极结构。