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1. 发明授权

US06417572B1 Process for producing metal interconnections and product produced thereby 有权
标题翻译：用于制造金属互连的方法和由此生产的产品
公开(公告)号：US06417572B1
公开(公告)日：2002-07-09
申请号：US09354592
申请日：1999-07-16
申请人： Dureseti Chidambarrao , Ronald G. Filippi , Robert Rosenberg , Thomas M. Shaw , Timothy D. Sullivan , Richard A. Wachnik
发明人： Dureseti Chidambarrao , Ronald G. Filippi , Robert Rosenberg , Thomas M. Shaw , Timothy D. Sullivan , Richard A. Wachnik
IPC分类号： H01L2348
CPC分类号： H01L23/528 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced. The process is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.
摘要翻译：一种制造具有绝缘钝化层的金属互连的多电平半导体器件的方法和由此产生的产品。该产品和工艺通过防止绝缘钝化层开裂而改善金属化互连对挤出 - 短电迁移故障的阻力。该产品和工艺也降低电阻饱和度或电迁移引起的最大电阻偏移。通过用绝缘钝化层包围的宽线金属化互连导电线，其两个或更多个狭窄的平行导线，其纵横比小于或等于位于其间的钝化层的单位，钝化裂纹和挤出 - 短路故障的发生率是减少该方法特别适用于多层布线结构，其中布线层具有由冗余金属化层，层间连接或两者引起的布线水平之间的扩散障碍。

2. 发明授权

US06202191B1 Electromigration resistant power distribution network 失效
标题翻译：防电力配电网络
公开(公告)号：US06202191B1
公开(公告)日：2001-03-13
申请号：US09333604
申请日：1999-06-15
申请人： Ronald G. Filippi , Phillip C. Lin , Thomas M. Shaw , Richard A. Wachnik
发明人： Ronald G. Filippi , Phillip C. Lin , Thomas M. Shaw , Richard A. Wachnik
IPC分类号： G06F1750
CPC分类号： H01L21/76858 , G06F17/5077 , H01L21/76841 , H01L21/7685 , H01L23/5286 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： Method for forming a novel power grid structure for integrated circuit semiconductor chip devices that exhibits increased electromigration resistance by including diffusion blocking interlevel contacts and employing a regular array of conducting line elements with “phase shift” between adjacent tracks of segmented power busses. The novel grid structure includes a first metal layer including a first set of conducting line segments that are substantially parallel to one another and run in a first direction; a layer of diffusion blocking dielectric insulation above the first layer; a second metal layer including a second set of conducting line segments substantially parallel to each other and running in a second direction orthogonal to the first direction; and, interlevel contact studs disposed substantially vertically through the diffusion blocking dielectric insulation layer for electrically connecting aligned line segments of the first and second sets, wherein each segment of the first and second sets of line segments is limited to a predetermined length by a diffusion blocking boundary.
摘要翻译：用于形成用于集成电路半导体芯片器件的新型电网结构的方法，其通过包括扩散阻挡层间接触并采用在分段功率总线的相邻轨道之间具有“相移”的导线组件的规则阵列来表现出增加的电迁移阻力。新颖的栅格结构包括第一金属层，其包括基本上彼此平行并沿第一方向延伸的第一组导线段; 在第一层之上的一层扩散阻挡介电绝缘层; 第二金属层，包括基本上彼此平行并沿与第一方向正交的第二方向延伸的第二组导线段; 以及穿过所述扩散阻挡介电绝缘层基本垂直设置的层间接触柱，用于电连接所述第一和第二组的对准的线段，其中所述第一和第二组线段的每个段通过扩散阻挡被限制到预定长度边界。

3. 发明授权

US06518670B1 Electrically porous on-chip decoupling/shielding layer 有权
标题翻译：多孔片上去耦/屏蔽层
公开(公告)号：US06518670B1
公开(公告)日：2003-02-11
申请号：US10091643
申请日：2002-03-06
申请人： Jack A. Mandelman , Ronald G. Filippi , Jeffrey P. Gambino , Richard A. Wachnik
发明人： Jack A. Mandelman , Ronald G. Filippi , Jeffrey P. Gambino , Richard A. Wachnik
IPC分类号： H01L2940
CPC分类号： H01L21/76897 , H01L23/5222 , H01L23/5228 , H01L23/5286 , H01L27/0802 , H01L27/0805 , H01L28/82 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes interconnected conductor lines comprising a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines are formed on the top surface of the lower ILD layer surrounded by an insulator formed on the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and it is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on a upper level. Each has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer is formed below the intermediate conductor to electrically insulate and separate the intermediate conductor lines from the lower conductor lines. A upper ILD layer overlies the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the upper conductor lines. The resistive stud, the capacitor dielectric, and the intermediate conductor across the capacitor dielectric layer and the liner layer form an electrically porous, distributed resistive-capacitive low-pass decoupling network.
摘要翻译：半导体器件包括互连的导体线，其包括在衬底上形成有顶表面的下层间介电层（ILD）层。在由形成在下ILD层上的绝缘体围绕的下ILD层的顶表面上形成几个下导体线。一组电阻螺柱中的每一个具有侧壁，下端和上端，并且在下端处连接到下导体线的顶部。在通过衬垫层和电容器电介质层从相邻螺柱分离的电阻螺柱之间形成几个中间导体线。上导体线形成在上层。每个具有与相应的一个电阻螺柱接触的底表面。在中间导体下方形成中心ILD层，以将中间导线与下导体线电绝缘和分离。上部ILD层覆盖中间导体，用于将中间导体线与上部导体线电绝缘和分离。电阻螺柱，电容器电介质和跨过电容器电介质层和衬层的中间导体形成电多孔分布式电阻电容低通去耦网络。

4. 发明申请

US20080231312A1 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US20080231312A1
公开(公告)日：2008-09-25
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

5. 发明授权

US07397260B2 Structure and method for monitoring stress-induced degradation of conductive interconnects 有权
标题翻译：用于监测导电互连的应力诱导退化的结构和方法
公开(公告)号：US07397260B2
公开(公告)日：2008-07-08
申请号：US11163948
申请日：2005-11-04
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

6. 发明授权

US07692439B2 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US07692439B2
公开(公告)日：2010-04-06
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

7. 发明授权

US07639032B2 Structure for monitoring stress-induced degradation of conductive interconnects 失效
标题翻译：用于监测导电互连的应力导致退化的结构
公开(公告)号：US07639032B2
公开(公告)日：2009-12-29
申请号：US12004011
申请日：2007-12-19
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

8. 发明授权

US06037795A Multiple device test layout 失效
标题翻译：多设备测试布局
公开(公告)号：US06037795A
公开(公告)日：2000-03-14
申请号：US938871
申请日：1997-09-26
申请人： Ronald G. Filippi , James J. Poulin , Robert D. Raviart , Kenneth P. Rodbell , Richard G. Smith , Timothy D. Sullivan , Alexander J. Swinton
发明人： Ronald G. Filippi , James J. Poulin , Robert D. Raviart , Kenneth P. Rodbell , Richard G. Smith , Timothy D. Sullivan , Alexander J. Swinton
IPC分类号： G01R31/28 , H01L23/544
CPC分类号： G01R31/2858 , G01R31/2853 , H01L22/34 , H01L2924/0002
摘要： A test layout increases the sample size of electromigration experiments. Through pad sharing, the number of structures tested can be increased, allowing hundreds of identical structures to be tested in a single high temperature oven door.
摘要翻译：测试布局增加了电迁移实验的样本量。通过垫共享，可以增加测试结构的数量，允许在单个高温烤箱门中测试数百个相同的结构。

9. 发明授权

US09059169B2 E-fuse structures and methods of manufacture 有权
标题翻译：电熔丝结构和制造方法
公开(公告)号：US09059169B2
公开(公告)日：2015-06-16
申请号：US13165087
申请日：2011-06-21
申请人： Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald G. Filippi , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon
发明人： Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald G. Filippi , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon
IPC分类号： H01L21/26 , H01L23/525 , H01L23/522 , H01L21/768
CPC分类号： H01L23/5256 , H01L21/768 , H01L21/76808 , H01L21/76811 , H01L21/76813 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.
摘要翻译：提供线后端的电熔丝结构（BEOL）互连和制造方法。该方法包括在衬底中与第一底层金属线对齐形成互连通孔，并在衬底中形成电熔丝通孔，露出第二下面的金属线。该方法还包括用第二底层金属线形成缺陷并用金属填充互连通孔并与第一底层金属线接触，从而形成互连结构。该方法还包括用金属填充e熔丝通孔并与缺陷和第二下面的金属线接触，从而形成电熔丝结构。

10. 发明授权

US08446014B2 Integrated circuit interconnect structure 失效
标题翻译：集成电路互连结构
公开(公告)号：US08446014B2
公开(公告)日：2013-05-21
申请号：US13531008
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

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