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1. 发明申请

US20120273966A1 INTEGRATED CIRCUIT INTERCONNECT STRUCTURE 失效
公开(公告)号：US20120273966A1
公开(公告)日：2012-11-01
申请号：US13531008
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

2. 发明授权

US08446014B2 Integrated circuit interconnect structure 失效
标题翻译：集成电路互连结构
公开(公告)号：US08446014B2
公开(公告)日：2013-05-21
申请号：US13531008
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

3. 发明授权

US08455351B2 Method of forming an integrated circuit interconnect structure 失效
标题翻译：形成集成电路互连结构的方法
公开(公告)号：US08455351B2
公开(公告)日：2013-06-04
申请号：US13531015
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中并且在其相对端处耦合到第一通孔的缓冲金属段。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

4. 发明申请

US20120264289A1 INTEGRATED CIRCUIT INTERCONNECT STRUCTURE 失效
标题翻译：集成电路互连结构
公开(公告)号：US20120264289A1
公开(公告)日：2012-10-18
申请号：US13531015
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

5. 发明授权

US08237286B2 Integrated circuit interconnect structure 有权
标题翻译：集成电路互连结构
公开(公告)号：US08237286B2
公开(公告)日：2012-08-07
申请号：US12760594
申请日：2010-04-15
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/522
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

6. 发明申请

US20110254168A1 INTEGRATED CIRCUIT INTERCONNECT STRUCTURE 有权
标题翻译：集成电路互连结构
公开(公告)号：US20110254168A1
公开(公告)日：2011-10-20
申请号：US12760594
申请日：2010-04-15
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/522 , H01L21/768 , G06F17/50
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

7. 发明申请

US20120175612A1 TEST STRUCTURE FOR DETERMINATION OF TSV DEPTH 有权
标题翻译：测定TSV深度的测试结构
公开(公告)号：US20120175612A1
公开(公告)日：2012-07-12
申请号：US13423823
申请日：2012-03-19
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L23/48
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.
摘要翻译：半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。

8. 发明授权

US08232115B2 Test structure for determination of TSV depth 有权
标题翻译：用于测定TSV深度的测试结构
公开(公告)号：US08232115B2
公开(公告)日：2012-07-31
申请号：US12566726
申请日：2009-09-25
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.
摘要翻译：半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括所述第一TSV，电连接到所述第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。

9. 发明授权

US08853693B2 Test structure for determination of TSV depth 有权
标题翻译：用于测定TSV深度的测试结构
公开(公告)号：US08853693B2
公开(公告)日：2014-10-07
申请号：US13423823
申请日：2012-03-19
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L21/00 , H01L21/768 , H01L21/66
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.
摘要翻译：半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。

10. 发明申请

US20110073858A1 Test Structure for Determination of TSV Depth 有权
标题翻译：测定TSV深度的测试结构
公开(公告)号：US20110073858A1
公开(公告)日：2011-03-31
申请号：US12566726
申请日：2009-09-25
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L23/48 , H01L21/66
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.
摘要翻译：半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括第一TSV，电连接到第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。

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