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1. 发明授权

US08446014B2 Integrated circuit interconnect structure 失效
标题翻译：集成电路互连结构
公开(公告)号：US08446014B2
公开(公告)日：2013-05-21
申请号：US13531008
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

2. 发明申请

US20120273966A1 INTEGRATED CIRCUIT INTERCONNECT STRUCTURE 失效
公开(公告)号：US20120273966A1
公开(公告)日：2012-11-01
申请号：US13531008
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

3. 发明授权

US08455351B2 Method of forming an integrated circuit interconnect structure 失效
标题翻译：形成集成电路互连结构的方法
公开(公告)号：US08455351B2
公开(公告)日：2013-06-04
申请号：US13531015
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中并且在其相对端处耦合到第一通孔的缓冲金属段。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

4. 发明申请

US20120264289A1 INTEGRATED CIRCUIT INTERCONNECT STRUCTURE 失效
标题翻译：集成电路互连结构
公开(公告)号：US20120264289A1
公开(公告)日：2012-10-18
申请号：US13531015
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

5. 发明授权

US08237286B2 Integrated circuit interconnect structure 有权
标题翻译：集成电路互连结构
公开(公告)号：US08237286B2
公开(公告)日：2012-08-07
申请号：US12760594
申请日：2010-04-15
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/522
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

6. 发明申请

US20110254168A1 INTEGRATED CIRCUIT INTERCONNECT STRUCTURE 有权
标题翻译：集成电路互连结构
公开(公告)号：US20110254168A1
公开(公告)日：2011-10-20
申请号：US12760594
申请日：2010-04-15
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/522 , H01L21/768 , G06F17/50
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

7. 发明授权

US06383920B1 Process of enclosing via for improved reliability in dual damascene interconnects 有权
标题翻译：封装通孔的过程可提高双镶嵌互连中的可靠性
公开(公告)号：US06383920B1
公开(公告)日：2002-05-07
申请号：US09757894
申请日：2001-01-10
申请人： Ping-Chuan Wang , Ronald G. Filippi , Robert D. Edwards , Edward W. Kiewra , Roy C. Iggulden
发明人： Ping-Chuan Wang , Ronald G. Filippi , Robert D. Edwards , Edward W. Kiewra , Roy C. Iggulden
IPC分类号： H01L214763
CPC分类号： H01L21/76847 , H01L21/76807 , H01L21/76811 , H01L21/76813 , H01L21/76843 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates generally to a method of enclosing a via in a dual damascene process. In one embodiment of the disclosed method, the via is etched first and a first barrier metal or liner is deposited in the via, the trench is then etched and a second barrier metal or liner is deposited in the trench, and finally the via and trench are filled or metallized in a dual damascene process, thereby forming a via or interconnect and a line. Alternatively, the trench may be etched first and a first barrier metal or liner deposited in the trench, then the via is etched and a second barrier metal or liner is deposited in the via, and finally the trench and via are filled or metallized in a dual damascene process. The barrier metal or liner encloses the via, thereby reducing void formation due to electromigration.
摘要翻译：本发明一般涉及在双镶嵌工艺中封闭通孔的方法。在所公开的方法的一个实施例中，首先蚀刻通孔，并且在通孔中沉积第一阻挡金属或衬垫，然后蚀刻沟槽，并且在沟槽中沉积第二阻挡金属或衬垫，最后沉积通孔和沟槽在双镶嵌工艺中填充或金属化，从而形成通孔或互连线。或者，可以首先蚀刻沟槽并且沉积在沟槽中的第一阻挡金属或衬垫，然后蚀刻通孔，并且在通孔中沉积第二阻挡金属或衬垫，最后将沟槽和通孔填充或金属化在双镶嵌工艺。阻挡金属或衬里封闭通孔，从而减少由于电迁移而导致的空隙形成。

8. 发明授权

US08465657B2 Post chemical mechanical polishing etch for improved time dependent dielectric breakdown reliability 有权
标题翻译：后化学机械抛光蚀刻，以提高时间依赖的介电击穿可靠性
公开(公告)号：US08465657B2
公开(公告)日：2013-06-18
申请号：US11833283
申请日：2007-08-03
申请人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewara , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewara , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01B13/00 , B44C1/22
CPC分类号： B24B37/042 , H01L21/31144 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L21/76852 , H01L21/76885 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204
摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.
摘要翻译：公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。释放层沉积在电介质层上。释放层包括有机材料，电介质材料，金属或金属氮化物。沟槽蚀刻到电介质层中。沟槽内衬衬里，填充导体。导体和衬里材料从剥离层抛光。然而，痕量的剩余材料可能会残留。去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

9. 发明申请

US20110193199A1 ELECTROMIGRATION IMMUNE THROUGH-SUBSTRATE VIAS 有权
标题翻译：电磁辐射穿过基底VIAS
公开(公告)号：US20110193199A1
公开(公告)日：2011-08-11
申请号：US12702463
申请日：2010-02-09
申请人： Ronald G. Filippi , John A. Fitzsimmons , Kevin Kolvenbach , Ping-Chuan Wang
发明人： Ronald G. Filippi , John A. Fitzsimmons , Kevin Kolvenbach , Ping-Chuan Wang
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/0657 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/00 , H01L2224/05552
摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.
摘要翻译：贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力。因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。

10. 发明授权

US07560375B2 Gas dielectric structure forming methods 失效
标题翻译：气体介电结构成型方法
公开(公告)号：US07560375B2
公开(公告)日：2009-07-14
申请号：US10711697
申请日：2004-09-30
申请人： Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang
发明人： Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76831 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening; depositing a conductive liner over the opening; depositing a metal in the opening; planarizing the metal and the conductive liner; removing the sacrificial layer sidewall to form a void; and depositing a cap layer over the void to form the gas dielectric structure. The invention is easily implemented in damascene wire formation processes, and improves structural stability.
摘要翻译：通过使用牺牲层形成用于半导体结构的气体电介质结构的方法。特别地，本发明的一个实施例包括在基板上的电介质层中形成用于半导体结构的开口; 在开口上沉积牺牲层; 在所述牺牲层上执行定向蚀刻以在所述开口上形成牺牲层侧壁; 在所述开口上沉积导电衬垫; 在开口中沉积金属; 平面化金属和导电衬垫; 去除牺牲层侧壁以形成空隙; 以及在所述空隙上沉积盖层以形成气体介电结构。本发明易于在镶嵌线形成过程中实现，并提高结构稳定性。

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