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1. 发明授权

US08836124B2 Fuse and integrated conductor 有权
标题翻译：保险丝和集成导体
公开(公告)号：US08836124B2
公开(公告)日：2014-09-16
申请号：US13414742
申请日：2012-03-08
申请人： Griselda Bonilla , Kaushik Chanda , Samuel Sung Shik Choi , Ronald G. Filippi , Stephan Grunow , Naftali Eliahu Lustig , Andrew H. Simon
发明人： Griselda Bonilla , Kaushik Chanda , Samuel Sung Shik Choi , Ronald G. Filippi , Stephan Grunow , Naftali Eliahu Lustig , Andrew H. Simon
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5256 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.
摘要翻译：熔丝结构包括在位于衬底之上的电介质层内的孔内，孔暴露在衬底内的导体接触层，介于导体接触层和另一导体层之间的晶种层。种子层包括掺杂的铜材料，其包括主要在种子层内固定的掺杂剂。可以切断熔丝结构，同时不切断也位于衬底上的导体互连结构，所述导体互连结构在第二孔内暴露第二导体接触层。与包括具有固定化掺杂剂的掺杂种子层的熔丝结构相反，互连结构包括具有可移动掺杂剂的掺杂种子层。

2. 发明申请

US20140070363A1 ELECTRONIC ANTI-FUSE 有权
标题翻译：电子防熔丝
公开(公告)号：US20140070363A1
公开(公告)日：2014-03-13
申请号：US13608183
申请日：2012-09-10
申请人： Junjing Bao , Griselda Bonilla , Samuel S. Choi , Ronald G. Filippi , Naftali Eliahu Lustig , Andrew H. Simon
发明人： Junjing Bao , Griselda Bonilla , Samuel S. Choi , Ronald G. Filippi , Naftali Eliahu Lustig , Andrew H. Simon
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An electronic anti-fuse structure, the structure including an Mx level comprising a first Mx metal and a second Mx metal, a dielectric layer located above the Mx level, an Mx+1 level located above the dielectric layer; and a metallic element in the dielectric layer and positioned between the first Mx metal and the second Mx metal, wherein the metallic element is insulated from both the first Mx metal and the second Mx metal.
摘要翻译：一种电子反熔丝结构，该结构包括包含第一Mx金属和第二Mx金属的Mx级，位于Mx级上方的电介质层，位于介电层上方的Mx + 1级; 以及金属元件，位于所述第一Mx金属和所述第二Mx金属之间，所述金属元件与所述第一Mx金属和所述第二Mx金属绝缘。

3. 发明申请

US20130307151A1 METHOD TO RESOLVE HOLLOW METAL DEFECTS IN INTERCONNECTS 有权
标题翻译：在互连中解决中空金属缺陷的方法
公开(公告)号：US20130307151A1
公开(公告)日：2013-11-21
申请号：US13472555
申请日：2012-05-16
申请人： Griselda Bonilla , Junjing Bao , Samuel S. Choi , Ronald G. Filippi , Naftali E. Lustig , Andrew H. Simon
发明人： Griselda Bonilla , Junjing Bao , Samuel S. Choi , Ronald G. Filippi , Naftali E. Lustig , Andrew H. Simon
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76849 , H01L21/76832 , H01L21/76834 , H01L23/5283 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.
摘要翻译：一种在互连和结构中修复空心金属空隙缺陷的方法。抛光互连后，中空金属空隙缺陷变得可见。缺陷的位置在很大程度上是可预测的。修复方法将掩模材料图案化成可能出现缺陷的互连（以及有时相邻的介电层）上的开口。在掩模孔中形成局部金属盖，以修复缺陷。电介质盖覆盖局部金属盖和形成在相邻电介质层中的任何凹陷。

4. 发明授权

US08378447B2 Electrically programmable fuse and fabrication method 有权
标题翻译：电可编程保险丝和制造方法
公开(公告)号：US08378447B2
公开(公告)日：2013-02-19
申请号：US13085632
申请日：2011-04-13
申请人： Kaushik Chanda , Ronald G. Filippi , Joseph M. Lukaitis , Ping-Chuan Wang
发明人： Kaushik Chanda , Ronald G. Filippi , Joseph M. Lukaitis , Ping-Chuan Wang
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.
摘要翻译：电可编程保险丝包括阳极，阴极和导电地连接阴极与阳极的熔断体，其可通过施加编程电流来编程。阳极和熔丝链路各自包括形成在多晶硅层上的多晶硅层和硅化物层，并且阴极包括多晶硅层和形成在阴极的多晶硅层的预定部分上的部分硅化物层，其位于阴极附近阴极和熔断体连接处的连接处。

5. 发明授权

US08304863B2 Electromigration immune through-substrate vias 有权
标题翻译：电迁移免疫穿透通孔
公开(公告)号：US08304863B2
公开(公告)日：2012-11-06
申请号：US12702463
申请日：2010-02-09
申请人： Ronald G. Filippi , John A. Fitzsimmons , Kevin Kolvenbach , Ping-Chuan Wang
发明人： Ronald G. Filippi , John A. Fitzsimmons , Kevin Kolvenbach , Ping-Chuan Wang
IPC分类号： H01L29/40
CPC分类号： H01L25/0657 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/00 , H01L2224/05552
摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.
摘要翻译：贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力。因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。

6. 发明申请

US20120249159A1 Stacked Via Structure For Metal Fuse Applications 有权
标题翻译：金属保险丝应用的堆叠通孔结构
公开(公告)号：US20120249159A1
公开(公告)日：2012-10-04
申请号：US13074407
申请日：2011-03-29
申请人： Ronald G. Filippi , Griselda Bonilla , Kaushik Chanda , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
发明人： Ronald G. Filippi , Griselda Bonilla , Kaushik Chanda , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
IPC分类号： G01R31/04 , G01R31/02 , H01L23/62
CPC分类号： H01L23/5226 , G01R31/025 , G01R31/04 , G01R31/07 , G01R31/327 , H01L23/5256 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53295 , H01L23/58 , H01L2924/0002 , H01L2924/00
摘要： A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.
摘要翻译：线路的后端（BEOL）保险丝结构具有一叠通孔。通孔的堆叠导致高的纵横比，使得通孔内的衬里和种子覆盖较差。衬里和种子层的弱点导致电迁移（EM）故障的较高概率。保险丝结构由于衬垫和种子覆盖不良而解决故障。设计特征允许确定故障发生的位置，确定熔丝编程之后受损区域的程度，并防止损坏的介质区域的进一步传播。

7. 发明授权

US08237283B2 Structure and method of reducing electromigration cracking and extrusion effects in semiconductor devices 失效
标题翻译：减少半导体器件中电迁移破裂和挤出效应的结构和方法
公开(公告)号：US08237283B2
公开(公告)日：2012-08-07
申请号：US11758206
申请日：2007-06-05
申请人： Kaushik Chandra , Ronald G. Filippi , Wai-Lin Li , Ping-Chuan Wang , Chih-Chao Yang
发明人： Kaushik Chandra , Ronald G. Filippi , Wai-Lin Li , Ping-Chuan Wang , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L23/528 , H01L21/7682 , H01L21/76831 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.
摘要翻译：用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在第二介电层中的空隙，停止在盖层上，其中，空隙以如下方式定位，以便隔离由于第一金属线的电迁移效应引起的结构损坏，包括一种或多种金属挤压的效果来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。

8. 发明申请

US20110254168A1 INTEGRATED CIRCUIT INTERCONNECT STRUCTURE 有权
标题翻译：集成电路互连结构
公开(公告)号：US20110254168A1
公开(公告)日：2011-10-20
申请号：US12760594
申请日：2010-04-15
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/522 , H01L21/768 , G06F17/50
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

9. 发明申请

US20110175226A1 INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING ENHANCED ELECTROMIGRATION RESISTANCE 有权
标题翻译：具有增强电阻率的集成电路的互连结构
公开(公告)号：US20110175226A1
公开(公告)日：2011-07-21
申请号：US12691213
申请日：2010-01-21
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76816 , H01L21/76846 , H01L21/76847 , H01L23/522 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line
摘要翻译：用于集成电路（IC）器件的互连结构包括形成在电介质层内的金属线，所述金属线在其中具有一个或多个垂直扩散阻挡层; 其中所述一个或多个垂直扩散屏障对应于在所述金属线上方形成的通孔的衬垫材料，所述通孔完全延伸穿过所述金属线的厚度，使得所述通孔的最底部包括所述金属线的一部分

10. 发明授权

US07737528B2 Structure and method of forming electrically blown metal fuses for integrated circuits 有权
标题翻译：为集成电路形成电熔金属保险丝的结构和方法
公开(公告)号：US07737528B2
公开(公告)日：2010-06-15
申请号：US12132337
申请日：2008-06-03
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Jeffrey P. Gambino , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Jeffrey P. Gambino , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
IPC分类号： H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.
摘要翻译：用于集成电路器件的熔丝结构包括限定在绝缘层内的细长金属互连层; 仅在所述金属互连层的顶表面的一部分上形成的金属盖层; 以及形成在所述金属盖层和所述金属互连层的其余部分上的电介质盖层，其不形成有所述金属盖层; 其中不具有形成在其上的金属覆盖层的金属互连层的其余部分容易受到电迁移故障机制的影响，以便通过施加通过细长金属互连层的电流来编程熔丝结构。

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